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51. 发明申请

US20150127875A1 PCI Express to PCI Express based low latency interconnect scheme for clustering systems 审中-公开
标题翻译：用于集群系统的PCI Express至基于PCI Express的低延迟互连方案
公开(公告)号：US20150127875A1
公开(公告)日：2015-05-07
申请号：US14588937
申请日：2015-01-03
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4282 , G06F13/4022 , G06F13/4221 , G06F2213/0026 , H04L49/40
摘要： PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
摘要翻译： PCI Express是一种总线或I / O互连标准，用于计算机或嵌入式系统内部，可实现更快的数据传输到外围设备。该标准仍在不断发展，但已经达到了一定程度的稳定性，使其他应用程序可以使用PCIE作为基础来实现。一种基于PCIE的互连方案，可实现多个支持PCIE的系统之间的交换和互连，每个PCIE系统都具有自己的PCIE根系，因此PCIE架构的可扩展性可以应用于连接系统之间的数据传输以形成系统集群。提出。这些连接的系统可以是任何计算，控制，存储或嵌入式系统。互连的可扩展性将允许集群在系统变得必要时增加带宽，而不改变到不同的连接体系结构。

52. 发明授权

US08811400B2 Method for identifying next hop 有权
标题翻译：识别下一跳的方法
公开(公告)号：US08811400B2
公开(公告)日：2014-08-19
申请号：US13385155
申请日：2012-02-06
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L12/28
CPC分类号： H04L47/24 , G06F13/4022 , G06F13/4282 , H04L45/74 , H04L47/125 , H04L49/25 , H04L69/32 , H04L69/324
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.
摘要翻译：数据链路帧或网络分组包含报头中的协议信息，并且可选地包含帧或分组的尾部。我们提出了一种方法，其中在另一个数据链路帧中单独传送与帧或分组相对应的协议信息的一部分或全部。 “单独发送的协议信息”被称为STPI。 STPI包含足够的协议信息来标识下一跳节点或端口。 STPI可以避免网络拥塞，提高链路效率。优选地，将存在对应于每个STPI的一个数据链路帧或网络分组，其包含数据和协议信息的其余部分，并且该帧/分组被称为DFoNP。 STPI和DFoNP的创建由帧或数据包的发起者完成，例如操作系统。

53. 发明申请

US20120226835A1 PCI Express to PCI Express based low latency interconnect scheme for clustering systems 审中-公开
标题翻译：用于集群系统的PCI Express至基于PCI Express的低延迟互连方案
公开(公告)号：US20120226835A1
公开(公告)日：2012-09-06
申请号：US13441883
申请日：2012-04-08
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G06F13/42
CPC分类号： G06F13/4282 , G06F13/4022 , G06F13/4221 , G06F2213/0026 , H04L49/40
摘要： PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between external systems, such that the scalability can be applied to enable data transport between connected systems to form a cluster of systems is proposed. These connected systems can be any computing or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.
摘要翻译： PCI Express是一种总线或I / O互连标准，用于计算机或嵌入式系统内部，可实现更快的数据传输到外围设备。该标准仍在不断发展，但已经达到了一定程度的稳定性，使其他应用程序可以使用PCIE作为基础来实现。提出了一种基于PCIE的互连方案，以实现外部系统之间的切换和互连，从而可以应用可扩展性来实现连接的系统之间的数据传输以形成系统集群。这些连接的系统可以是任何计算或嵌入式系统。互连的可扩展性将允许集群在系统变得必要时增加带宽，而不改变到不同的连接体系结构。

54. 发明授权

US07606248B1 Method and apparatus for using multiple network processors to achieve higher performance networking applications 有权
标题翻译：使用多个网络处理器来实现更高性能的网络应用的方法和设备
公开(公告)号：US07606248B1
公开(公告)日：2009-10-20
申请号：US10144387
申请日：2002-05-10
申请人： Greg Maturi , Neil Mammen , Sagar Edara , Mammen Thomas
发明人： Greg Maturi , Neil Mammen , Sagar Edara , Mammen Thomas
IPC分类号： H04L12/56
CPC分类号： H04L47/10
摘要： An apparatus is described having a plurality of network processors that identify, for each of a plurality of packets, which multidimensional queue from amongst a plurality of multidimensional queues that each one of the plurality of packets should be enqueued into. Each of the network processors is able to identify a particular multidimensional queue for a different one of the plurality of packets.
摘要翻译：描述了一种装置，其具有多个网络处理器，其针对多个分组中的每一个识别从多个多维队列中的每个多个分组应该入队的多维队列。每个网络处理器能够识别多个分组中的不同分组的特定多维队列。

55. 发明申请

US20080081410A1 Multi-bit memory technology (MMT) and cells 有权
标题翻译：多位存储技术（MMT）和单元格
公开(公告)号：US20080081410A1
公开(公告)日：2008-04-03
申请号：US11541080
申请日：2006-10-02
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： H01L21/8242
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/66833
摘要： As the process development has matured and technology has scaled to smaller and smaller dimensions, the Poly-silicon floating gate cell is approaching its scaling limitations, multi-bit storage in a single memory cell has become the norm. The use of a Nitride layer or a silicon-nodule layer capable of location specific charge storage with no spreading, allows easy implementation of multi-bit technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element. If charge is stored in layer of discrete silicon-nodules separated by a thin insulating film, an Oxide silicon-nodule Oxide storage element is used as the storage layer.The multi-bit cells proposed are programmed by hot electron programming and erased either by using high Voltage tunneling, or by use of a lower voltage MIM Metal-Insulator-Metal Diode carrier generation method and technology called the Tunnel-Gun or TG.
摘要翻译：随着工艺开发成熟，技术已经缩小到更小和更小的尺寸，多晶硅浮栅单元正在接近其定标限制，单个存储单元中的多位存储已成为常规。使用不扩散的能够定位电荷存储的氮化物层或硅结核层，容易实现多位技术。如果电荷存储在氮化物存储层中的陷阱中，则使用氧化氮氮化物作为存储元件。如果电荷存储在由薄绝缘膜分离的离散硅结晶层中，则使用氧化物硅结节氧化物存储元件作为存储层。所提出的多位单元通过热电子编程进行编程，并通过使用高电压隧穿或者通过使用较低电压的金属 - 绝缘体 - 金属二极管载流子生成方法和称为隧道枪或TG的技术进行擦除。

56. 发明授权

US07336669B1 Mechanism for distributing statistics across multiple elements 有权
标题翻译：跨多个元素分配统计的机制
公开(公告)号：US07336669B1
公开(公告)日：2008-02-26
申请号：US10151774
申请日：2002-05-20
申请人： Neil Mammen , Sagar Edara , Mammen Thomas , Greg Maturi
发明人： Neil Mammen , Sagar Edara , Mammen Thomas , Greg Maturi
IPC分类号： H04L12/28
CPC分类号： H04L43/02
摘要： According to one embodiment, a network is disclosed. The network includes a source device, a networking hardware machine coupled to the source device, and a destination device coupled to the networking hardware machine. The networking hardware machine receives data packets from the source device and distributes statistics data corresponding to the data packets among multiple internal memory devices.
摘要翻译：根据一个实施例，公开了一种网络。网络包括源设备，耦合到源设备的网络硬件机器以及耦合到网络硬件机器的目的地设备。网络硬件机器从源设备接收数据包，并在多个内部存储设备之间分配与数据包相对应的统计数据。

57. 发明申请

US20080042184A1 Highly reliable NAND flash memory using five side enclosed floating gate storage elements 有权
标题翻译：高可靠性的NAND闪存采用五面封闭的浮动存储单元
公开(公告)号：US20080042184A1
公开(公告)日：2008-02-21
申请号：US11506026
申请日：2006-08-18
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： H01L29/76
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the quantum of charge stored to provide reconstruction of data. Such a memory made with a floating gate that is spaced away from the diffusions and covered on all five sides except the channel side, by the control gate, there by having increased coupling with the associated advantage of lower high voltages, reduced impact of the unwanted disturb conditions, and providing for improved retention and reliability characteristics at higher operating temperatures is disclosed. The main emphasis in this technology is to provide a device with improved retention, endurance, and temperature characteristics meeting the Automotive specifications even with some area penalty.
摘要翻译：具有排列在NAND串中的诸如浮动栅极的单个电荷存储元件阵列的NAND闪速存储器系统，每个元件能够在程序或擦除操作期间以其中的电荷形式选择性地存储数据，以及在读取操作期间感测存储的电荷量以提供数据的重建。这样的存储器由浮动栅极制成，该浮动栅极与扩散部分隔开，并且通过控制栅极覆盖除通道侧以外的所有五个侧面，通过增加与较低高电压相关联的优点的耦合，减少不需要的公开了在更高的操作温度下提供改进的保持和可靠性特性的干扰条件。该技术的主要重点是提供一种具有符合汽车规格的保留，耐久性和温度特性的设备，即使有一些区域损失。

58. 发明授权

US07193900B2 CACT-TG (CATT) low voltage NVM cells 失效
标题翻译： CACT-TG（CATT）低电压NVM电池
公开(公告)号：US07193900B2
公开(公告)日：2007-03-20
申请号：US11037742
申请日：2005-01-18
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0458 , G11C16/12 , G11C16/14 , H01L27/11556
摘要： Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type of carriers in the floating gate, and another method, the Tunnel Gun (TG) method, for accumulating the other type of carriers in the floating gate of the cells. These methods use low applied voltages to program and erase the Non-Volatile Memory cell. The proposed CATT (CAcT-Tg) cells by elimination of high voltage requirements are scalable with technology and easily manufacturable using current processes technologies. These cells also have multi-bit storage capability as the program erase methods used are self-limiting in character. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.
摘要翻译：这里描述了用于编程和擦除NVM单元的CACT和TG非易失性程序擦除方法。这种组合允许使用低电压方法进行程序和擦除。所描述的典型单元使用“用于编程存储器的通道加速载波隧道（CACT）方法”用于在浮动栅极中累积一种类型的载波，另一种方法是隧道炮（TG）方法，用于将其他类型的载波累加电池的浮动门。这些方法使用低施加电压来编程和擦除非易失性存储单元。通过消除高电压要求，提出的CATT（CAcT-Tg）电池可通过技术进行扩展，并可使用当前工艺技术轻松制造。这些单元还具有多位存储能力，因为使用的程序擦除方法是自限制的。另一个优点是由于降低的电压应力，使用这种方法增加了电池的可靠性。

59. 发明授权

US07149125B1 Location-specific NAND (LS NAND) memory technology and cells 有权
标题翻译：位置特定NAND（LS NAND）存储器技术和单元
公开(公告)号：US07149125B1
公开(公告)日：2006-12-12
申请号：US11334790
申请日：2006-01-19
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/12 , G11C16/16 , H01L27/115 , H01L27/11521 , H01L29/7881
摘要： The use of a Nitride layer or a silicon-nodule layer capable of Location-Specific (LS) charge storage, allow easy vertical scaling and implementation of NOR and NAND NVM array and technology. If the charge is stored in the traps in the Nitride storage layer, a Oxide Nitride Oxide is used as the storage element and if charge is stored in potential wells of discrete silicon-nodules, or Carbon Buckyball layers, an Oxide silicon-nodule Oxide storage element, or an Oxide Buckyball Oxide layer is used as the storage element.The problem of Location-Specific NAND memory is the inability to erase the cells with repeatable results. A novel erase method, Tunnel Gun (TG) method, that generate holes for consistent erase of LS storage elements and typical NAND Cells that erase by the disclosed method and programmed by either by Fouler-Nordheim (FN) tunneling or Low Current Hot Electron (LCHE) method are disclosed.
摘要翻译：使用能够定位特定（LS）电荷存储的氮化物层或硅结节层，可以轻松地垂直缩放和实现NOR和NAND NVM阵列和技术。如果电荷存储在氮化物存储层中的陷阱中，则使用氧化氮氮氧化物作为存储元件，并且如果电荷存储在离散硅结节或碳黑球层的潜在阱中，则氧化物硅结节氧化物存储元素或氧化物巴克球氧化物层用作存储元件。位置特定的NAND存储器的问题是无法用可重复的结果擦除单元。一种新颖的擦除方法，隧道枪（TG）方法，其产生用于LS存储元件和典型NAND单元的一致擦除的空穴，该NAND存储元件通过所公开的方法擦除并由Fouler-Nordheim（FN）隧道或低电流热电子 LCHE）方法。

60. 发明授权

US5519653A Channel accelerated carrier tunneling-(CACT) method for programming memories 失效
标题翻译：用于编程存储器的信道加速载波隧道（CACT）方法
公开(公告)号：US5519653A
公开(公告)日：1996-05-21
申请号：US209787
申请日：1994-03-11
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G11C16/10 , H01L29/423 , H01L29/788 , G11C11/34
CPC分类号： H01L29/42324 , G11C16/10 , H01L29/7885
摘要： A Channel Accelerated Carrier Tunneling method of programming high speed, low voltage, memory cells, typically non-volatile memory cells, using the majority carriers available in an MOS channel is disclosed. The method uses the velocity of the majority carriers in the channel, the kinetic energy available, to enhance the accelerating voltage applied towards a storage electrode to enhance the collection and storage of the carriers by the storage electrode, typically a floating gate in a non-volatile memory. The method envisages a discontinuity in the channel which allows the carriers to be accelerated towards it. By having a storage electrode with voltage gradient, over lying the discontinuity, in the direction of acceleration of the carriers, these carriers can be made to pass through the oxide barrier of the gate and accumulate on the storage node. The use of the acceleration of the carriers allow the additional applied field requirement, to cause tunneling, to be lower and hence the voltages applied to the control gate can be lower in value. In addition the availability of the large population of majority carriers in the channel under operating conditions of voltage and current, having the correct directional velocity component, allows the memory to be written at high speeds. The large number of channel majority carriers also allow the use of lower junction voltages in the device, as no additional carrier generation by alternate methods, like impact ionization, is needed. This in effect allows the manufacture of high speed, low voltage memory cells for applications in high density memories. The use of low fields and low voltages also tend to enhance the reliability of the cells by reducing the stresses on the device elements.
摘要翻译：公开了使用MOS通道中可用的多数载波来编程高速，低电压，存储单元（通常为非易失性存储单元）的信道加速载波隧道方法。该方法使用通道中的多数载流子的速度，可用的动能来增强施加到存储电极的加速电压，以增强存储电极（通常是非栅极的浮置栅极）对载流子的收集和存储，易失性存储器该方法设想在通道中的不连续性，其允许载体朝向其加速。通过具有电压梯度的存储电极，在不连续的位置上，在载流子的加速方向上，可以使这些载流子通过栅极的氧化物屏障并积累在存储节点上。使用载波的加速度允许额外的施加的场要求使得隧道效率降低，因此施加到控制栅极的电压的值可以较低。另外，在具有正确的方向速度分量的电压和电流的操作条件下，通道中大量载波的大量载波的可用性允许以高速写入存储器。大量的通道多数载流子还允许在器件中使用较低的结电压，因为不需要通过替代方法（如冲击电离）产生另外的载流子。这实际上允许制造用于高密度存储器中的高速，低电压存储单元。低电场和低电压的使用也倾向于通过减少器件元件上的应力来提高电池的可靠性。

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