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51. 发明申请

US20080133627A1 LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件的大型多路复用器
公开(公告)号：US20080133627A1
公开(公告)日：2008-06-05
申请号：US11566982
申请日：2006-12-05
申请人： Martin Langhammer , Kumara Tharmalingam
发明人： Martin Langhammer , Kumara Tharmalingam
IPC分类号： G06F7/57 , G06F17/00
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
摘要翻译：可编程逻辑器件中的多个专用处理块，包括用于将这些乘法器的结果相加的乘法器和电路的多个专用处理块可以被配置为较大的乘法器，通过将添加到专用处理块的可选择电路来移位乘法器结果。在一个实施例中，这允许在专门的处理块中进行除最终添加之外的所有添加，最后的加法发生在可编程逻辑中。在另一个实施例中，附加的压缩和加法电路甚至允许在专门的处理块中发生最后的添加。

52. 发明授权

US07230451B1 Programmable logic device with routing channels 有权
标题翻译：具有路由通道的可编程逻辑器件
公开(公告)号：US07230451B1
公开(公告)日：2007-06-12
申请号：US11208906
申请日：2005-08-22
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be programmably selectively chained, wherein each functional unit contains an operational block and output selection logic that are configured to programmably selectively implement any of a variety of operations (e.g., bitwise, logical, arithmetic, etc.) that may be performed on the outputs of single FSBs and/or several FSBs. In addition to the output routing channel, the PLD includes at least one input routing channel that is configured to facilitate the routing, registering, and/or selection of FSB input signals. The FSB input routing channel also includes circuitry for performing elementary processing operations.
摘要翻译：提供了一种可编程逻辑器件（PLD），其包括至少一个专用输出路由通道，其被配置为便于处理由多个功能特定块（FSB）产生的输出信号。输出路由信道包括可编程选择性链接的多个功能单元，其中每个功能单元包含操作块和输出选择逻辑，其被配置为可编程选择性地执行各种操作（例如，按位，逻辑，运算等），其可以在单个FSB和/或几个FSB的输出上执行。除了输出路由信道之外，PLD还包括至少一个输入路由信道，其被配置为便于FSB输入信号的路由，注册和/或选择。 FSB输入路由信道还包括用于执行基本处理操作的电路。

53. 发明授权

US07142011B1 Programmable logic device with routing channels 有权
公开(公告)号：US07142011B1
公开(公告)日：2006-11-28
申请号：US11239735
申请日：2005-09-29
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17732
摘要： A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be programmably selectively chained, wherein each functional unit contains an operational block and output selection logic that are configured to programmably selectively implement any of a variety of operations (e.g., bitwise, logical, arithmetic, etc.) that may be performed on the outputs of single FSBs and/or several FSBs. In addition to the output routing channel, the PLD may also contain at least one input routing channel that is configured to facilitate the routing, registering, and/or selection of FSB input signals. In some cases, the FSB input routing channel may also include circuitry for performing elementary processing operations.

54. 发明授权

US07109895B1 High performance Lempel Ziv compression architecture 有权
标题翻译：高性能Lempel Ziv压缩架构
公开(公告)号：US07109895B1
公开(公告)日：2006-09-19
申请号：US11049072
申请日：2005-02-01
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H03M7/34
CPC分类号： H03M7/3088 , H03M7/3084
摘要： A data compression architecture includes a shift register with multiple shift register elements. A data input receives input data characters, and applies each received input data character to the shift register, such that the received input data character is stored in each shift register element of said shift register in turn. Logic circuitry is associated with each shift register element of the shift register, for detecting a match when the comparison circuitry determines that a sequence of two or more received input data characters is equal to a sequence stored in the shift register. A flush input receives a data flush input signal, and applies a received data flush input signal to the logic circuitry associated with each shift register element of the shift register, such that no match is detected by said logic circuitry when the data flush input signal is received.
摘要翻译：数据压缩架构包括具有多个移位寄存器元件的移位寄存器。数据输入接收输入数据字符，并将每个接收到的输入数据字符应用于移位寄存器，使得所接收的输入数据字符依次存储在所述移位寄存器的每个移位寄存器元件中。逻辑电路与移位寄存器的每个移位寄存器元件相关联，用于当比较电路确定两个或多个接收到的输入数据字符的序列等于存储在移位寄存器中的序列时检测匹配。冲洗输入接收数据刷新输入信号，并将接收到的数据刷新输入信号施加到与移位寄存器的每个移位寄存器元件相关联的逻辑电路，使得当数据刷新输入信号为收到了

55. 发明授权

US07084664B1 Integrated circuits with reduced interconnect overhead 失效
标题翻译：具有减少互连开销的集成电路
公开(公告)号：US07084664B1
公开(公告)日：2006-08-01
申请号：US10867456
申请日：2004-06-14
申请人： Kwan Yee Lee , Martin Langhammer , Ali H. Burney
发明人： Kwan Yee Lee , Martin Langhammer , Ali H. Burney
IPC分类号： G06F7/38 , H03K19/173 , H04Q7/00 , H04Q7/28
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17784
摘要： Integrated circuits are provided that use on-chip data compression and decompression to minimize consumption of interconnect resources. Parallel-to-serial converter circuitry can use time-division multiplexing techniques to compress data. The compressed data may be conveyed between circuit blocks on the integrated circuit using a reduced number of parallel interconnect conductors. After the compressed data has been conveyed to its destination, a serial-to-parallel converter may use time-division demultiplexing techniques to decompress the data. Interconnect resources may be shared by dedicated circuits. With this arrangement, signals can be selectively steered through the appropriate dedicated circuitry to either maximize performance or to use compression and decompression to minimize interconnect resource consumption.
摘要翻译：提供了使用片上数据压缩和解压缩以最小化互连资源消耗的集成电路。并行到串行转换器电路可以使用时分复用技术来压缩数据。压缩数据可以使用减少数量的并联互连导体在集成电路上的电路块之间传送。在将压缩数据传送到其目的地之后，串行到并行转换器可以使用时分解复用技术来解压缩数据。互连资源可以由专用电路共享。通过这种安排，可以通过适当的专用电路选择性地控制信号，以最大化性能或使用压缩和解压缩来最小化互连资源消耗。

56. 发明申请

US20060103419A1 Programmable logic device including multipliers and configurations thereof to reduce resource utilization 有权
公开(公告)号：US20060103419A1
公开(公告)日：2006-05-18
申请号：US11319846
申请日：2005-12-28
申请人： Martin Langhammer , Chiao Hwang , Gregory Starr
发明人： Martin Langhammer , Chiao Hwang , Gregory Starr
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , G06F7/523 , G06F2207/3816 , H03K19/17728 , H03K19/17732
摘要： In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

57. 发明授权

US07003544B1 Method and apparatus for generating a squared value for a signed binary number 失效
标题翻译：用于生成有符号二进制数的平方值的方法和装置
公开(公告)号：US07003544B1
公开(公告)日：2006-02-21
申请号：US10145322
申请日：2002-05-14
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/552
CPC分类号： G06F7/552 , G06F2207/5523
摘要： A squaring circuit for signed binary numbers includes a signed binary number modification unit that generates a modified signed binary number. The squaring circuit includes a partial product generation unit that generates partial products that make up a squared value of the modified signed binary number. The squaring circuit includes a correction value generation unit that generates a correction value for the signed binary number. The squaring circuit includes a summing unit that sums the partial products with the correction value to generate a squared value for the signed binary number.
摘要翻译：用于带符号二进制数的平方电路包括生成修改后的带符号二进制数的有符号二进制数修改单元。平方电路包括产生构成经修改的带符号二进制数的平方值的部分乘积的部分乘积生成单元。平方电路包括校正值生成单元，其生成用于有符号二进制数的校正值。平方电路包括求和单元，其将部分乘积与校正值相加以生成用于带符号二进制数的平方值。

58. 发明授权

US06400290B1 Normalization implementation for a logmap decoder 有权
标题翻译：日志对照解码器的规范化实现
公开(公告)号：US06400290B1
公开(公告)日：2002-06-04
申请号：US09511206
申请日：2000-02-23
申请人： Martin Langhammer , Volker Mauer
发明人： Martin Langhammer , Volker Mauer
IPC分类号： H03M1300
CPC分类号： H03M13/3905 , H03M13/6583
摘要： A programmable logic device can be programmed to configure its logic elements to approximate the normalization of probability values used in the operation of logMAP decoders, thereby significantly reducing the amount of logic resources required in the normalization procedure without significantly degrading performance. In the first preferred embodiment, normalization is achieved by approximating the normalization value by calculating an approximate normalization value which is then deducted from all &agr; values in the trellis at any time. This is done by logically ANDing all &agr; input probability values with the NOT of their own MSBs. The resulting outputs are then all bitwise ORed together, the output of which is the approximate normalization value. In another embodiment, the approximate normalization value is calculated using a fixed constant determinable at the outset of the logMAP decoder operation.
摘要翻译：可编程逻辑器件可以配置其逻辑元件来近似在logMAP解码器的操作中使用的概率值的归一化，从而显着减少归一化过程中所需的逻辑资源量，而不会显着降低性能。在第一优选实施例中，通过近似归一化值来实现归一化，即通过计算随后从网格中的所有α值中扣除的近似归一化值。这是通过将所有alpha输入概率值与其自己的MSB的NOT进行逻辑与运算来完成的。所得到的输出随后全部按位或相加在一起，其输出是近似归一化值。在另一个实施例中，使用在logMAP解码器操作开始时可确定的固定常数来计算近似归一化值。

59. 发明申请

US20200327271A1 FPGA Specialist Processing Block for Machine Learning 审中-公开
公开(公告)号：US20200327271A1
公开(公告)日：2020-10-15
申请号：US16914009
申请日：2020-06-26
申请人： Martin Langhammer , Dongdong Chen , Jason R. Bergendahl
发明人： Martin Langhammer , Dongdong Chen , Jason R. Bergendahl
IPC分类号： G06F30/34 , G06F30/38 , G06F9/30 , G06N20/00
摘要： The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

60. 发明授权

US09164728B1 Ternary DSP block 有权
标题翻译：三进制DSP模块
公开(公告)号：US09164728B1
公开(公告)日：2015-10-20
申请号：US13471951
申请日：2012-05-15
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/53
CPC分类号： G06F7/5324 , G06F7/4812 , G06F2207/3812
摘要： Backwards compatible architecture for improving the arithmetic capability of existing processing blocks for relatively low cost is disclosed. The architecture includes a processing block on an integrated circuit device. The processing block includes a first, a second, and a third configurable multiplier and a configurable adder network. The processing block also includes a configurable interconnect within the processing block for routing signals between each of the multipliers and the adder network in accordance with a mode of operation. One or more of the processing blocks may be used to perform compute various calculations such as complex number multiplication and/or real number multiplication. The calculations may be performed on input values contain various numbers of bits, such as 36 bit numbers, 54 bit numbers, or 72 bit numbers.
摘要翻译：公开了用于以相对低的成本提高现有处理块的算术能力的向后兼容架构。该架构包括集成电路装置上的处理块。处理块包括第一，第二和第三可配置乘法器和可配置加法器网络。处理块还包括处理块内的可配置互连，用于根据操作模式在每个乘法器和加法器网络之间路由信号。可以使用一个或多个处理块来执行计算各种计算，例如复数乘法和/或实数乘法。可以对包含各种位数（例如36位数，54位数或72位数）的输入值执行计算。

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