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51. 发明授权

US08885400B2 Compensation scheme for non-volatile memory 有权
公开(公告)号：US08885400B2
公开(公告)日：2014-11-11
申请号：US13773078
申请日：2013-02-21
申请人： SanDisk 3D LLC
发明人： Yingchang Chen , Pankaj Kalra , Chandrasekhar Gorla
IPC分类号： G11C13/00 , G11C7/00 , G11C11/56
CPC分类号： G11C7/12 , G11C7/00 , G11C11/56 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0076
摘要： Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

52. 发明授权

US08883655B2 Atomic layer deposition of metal oxide materials for memory applications 有权
标题翻译：用于记忆应用的金属氧化物材料的原子层沉积
公开(公告)号：US08883655B2
公开(公告)日：2014-11-11
申请号：US13897050
申请日：2013-05-17
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Vidyut Gopal , Imran Hashim , Dipankar Pramanik
IPC分类号： H01L21/31 , H01L21/469 , H01L45/00 , H01L21/02 , C23C16/455 , C23C16/40 , H01L27/24
CPC分类号： H01L45/145 , C23C16/40 , C23C16/45525 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/2463 , H01L45/08 , H01L45/1266 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.
摘要翻译：本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。设置在金属氧化物层之间的界面有助于氧空位移动。在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。因此，氧空缺在切换期间被捕获和释放，而空位明显损失。因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

53. 发明申请

US20140328105A1 METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 有权
标题翻译：用于降低成本花纹的三维矩阵阵列存储器的布局方法和装置
公开(公告)号：US20140328105A1
公开(公告)日：2014-11-06
申请号：US14334653
申请日：2014-07-17
申请人： SanDisk 3D LLC
发明人： Roy E. Scheuerlein , Christopher J. Petti , Yoichiro Tanaka
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.
摘要翻译：为三维存储器的存储器层布局提供了装置，方法和系统。存储层包括多个存储器阵列块; 耦合到其上的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。存储器线从存储器阵列块延伸，使用侧壁限定的工艺形成，并且半间距尺寸小于形成存储器线的光刻工具的标称最小特征尺寸能力。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。存储线被布置成允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供在其它存储器线路之间的区域的图案。公开其他方面。

54. 发明申请

US20140319443A1 Sequential Atomic Layer Deposition of Electrodes and Resistive Switching Components 有权
标题翻译：电极和电阻式开关元件的顺序原子层沉积
公开(公告)号：US20140319443A1
公开(公告)日：2014-10-30
申请号：US14327774
申请日：2014-07-10
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Tim Minvielle , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/2481 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16 , H01L45/1616
摘要： Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.
摘要翻译：提供了使用原子层沉积技术形成非易失性存储元件的方法，其中存储元件的至少两个不同层顺次沉积并且在沉积室中不破坏真空。该方法可以用于防止用于电极的各种材料的氧化，而不需要单独的氧阻隔层。可以使用信号线和电阻开关层的组合来封盖电极并使其氧化最小化。因此，存储元件中需要更少的层。此外，原子层沉积允许更精确地控制电极厚度。在一些实施例中，电极的厚度可以小于50埃。总的来说，电极和电阻开关层的原子层沉积导致整个存储元件的较小厚度，使得它们更适合于高级节点的低纵横比特征。

55. 发明申请

US20140315369A1 Resistive Random Access Memory Cells Having METAL ALLOY Current Limiting layers 有权
标题翻译：具有金属合金电流限制层的电阻随机存取存储器单元
公开(公告)号：US20140315369A1
公开(公告)日：2014-10-23
申请号：US14317155
申请日：2014-06-27
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim , Tim Minvielle , Dipankar Pramanik , Takeshi Yamaguchi
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16
摘要： Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.
摘要翻译：提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由过渡金属的合金形成的限流层。这种合金的一些实例包括还可以包括镍，铝和/或硅的含铬合金。其它实例包括也可以包括硅和碳的组合或铝和氮的组合的含钽和/或钛的合金。这些限流层可具有至少约1欧姆 - 厘米的电阻率。即使当这些层受到强电场和/或高温处理时，也保持该电阻率水平。在一些实施例中，限流层的击穿电压为至少约8V。层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

56. 发明申请

US20140301130A1 VERTICAL CROSS POINT RERAM FORMING METHOD 有权
标题翻译：垂直交叉点RERAM形成方法
公开(公告)号：US20140301130A1
公开(公告)日：2014-10-09
申请号：US14246052
申请日：2014-04-05
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, a plurality of forming operations may be performed in which non-volatile storage elements located near the far end of a plurality of word line fingers associated with a word line comb are formed prior to forming other non-volatile storage elements. In one example, non-volatile storage elements may be formed in each of the plurality of word line fingers in parallel and in an order that forms non-volatile storage elements in each of the plurality of word line fingers that are located near the far ends of the plurality of word line fingers before forming other non-volatile storage elements. Each non-volatile storage element that is formed during a forming operation may be current limited while a forming voltage is applied across the non-volatile storage element.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，可以执行多个形成操作，其中在形成其他非易失性存储元件之前形成位于与字线梳相关联的多个字线手指的远端附近的非易失性存储元件。在一个示例中，非易失性存储元件可以并行地形成在多个字线手指中的每一个中，并且以在多个字线手指中的远端附近形成非易失性存储元件的顺序在形成其他非易失性存储元件之前的多个字线指。在成形操作期间形成的每个非易失性存储元件可以是电流限制的，同时在非易失性存储元件上施加形成电压。

57. 发明授权

US08842468B2 Load and short current measurement by current summation technique 有权
公开(公告)号：US08842468B2
公开(公告)日：2014-09-23
申请号：US13754801
申请日：2013-01-30
申请人： Sandisk 3D, LLC
发明人： Vincent Lai
IPC分类号： G11C11/00 , G11C5/14 , G11C13/00 , G11C7/00
CPC分类号： G11C5/147 , G11C7/00 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/025 , G11C29/50 , G11C2013/0052 , G11C2013/0088 , G11C2013/0092 , G11C2029/0409 , G11C2029/1202 , G11C2029/1204 , G11C2029/5006 , G11C2213/71 , G11C2213/77
摘要： Methods for monitoring one or more load currents corresponding with one or more voltage regulators used during operation of a semiconductor memory are described. The one or more load currents may be due to the biasing of memory cells within a memory array or due to the presence of shorts between lines in the memory array. A plurality of load currents corresponding with a plurality of voltage regulators may be monitored in real-time before and during biasing of one or more memory arrays. The plurality of load currents may be monitored using a configurable load current monitoring circuit that uses a current summation technique. The ability to monitor the plurality of load currents before performing a programming operation on a memory array allows for remapping of defective portions of the memory array and modification of programming bandwidth prior to the programming operation.

58. 发明授权

US08836412B2 Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple 有权
公开(公告)号：US08836412B2
公开(公告)日：2014-09-16
申请号：US14101164
申请日：2013-12-09
申请人： SanDisk 3D LLC
发明人： Kesheng Wang , Ali Al-Shamma
IPC分类号： G05F1/10 , G05F3/02 , H03L7/08
CPC分类号： G11C5/145 , G11C7/04 , G11C7/22 , H02M3/07 , H03L7/0802
摘要： A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

59. 发明申请

US20140254231A1 3D Non-Volatile Memory Having Low-Current Cells and Methods 有权
标题翻译：具有低电流电池的3D非易失性存储器和方法
公开(公告)号：US20140254231A1
公开(公告)日：2014-09-11
申请号：US14196956
申请日：2014-03-04
申请人： SanDisk 3D LLC
发明人： Raul Adrian Cernea , Yung-Tin Chen , George Samachisa
IPC分类号： G11C5/06 , G11C13/00 , H01L45/00
CPC分类号： G11C5/06 , G11C5/025 , G11C5/04 , G11C13/0002 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149
摘要： A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described.
摘要翻译：非易失性存储器的3D阵列具有在字线和位线之间的交叉处访问的每个读/写元件。读/写元件形成具有包围氧化物核心的R / W材料的外壳的管状电极。在矩形形式中，电极的一侧接触字线，另一侧接触位线。壳体的厚度而不是与字线和位线接触的表面积决定了传导截面，因此决定了电阻。通过调整外壳的厚度，独立于与字线或位线的接触面积，每个读/写元件可以以大大增加的电阻工作，因此电流大大降低。还描述了使用这种管状R / W元件3D阵列来制造3D阵列的过程。

60. 发明申请

US20140252454A1 VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION 有权
标题翻译：用于高电压操作的垂直位线TFT解码器
公开(公告)号：US20140252454A1
公开(公告)日：2014-09-11
申请号：US13788990
申请日：2013-03-07
申请人： SANDISK 3D LLC
发明人： Peter Rabkin , Masaaki Higashitani
IPC分类号： H01L27/105
CPC分类号： H01L27/1052 , G11C13/0002 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2213/71 , H01L27/11551 , H01L27/11578 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.
摘要翻译：公开了一种具有垂直取向的薄膜晶体管（TFT）选择装置的3D存储器阵列，其具有通道延伸，否则称为栅极/结偏移。具有通道扩展的垂直取向的TFT选择装置用作3D存储器阵列中的垂直位线选择装置。具有通道延伸的垂直TFT选择装置具有高击穿电压和低漏电流。沟道延伸可以在TFT的顶部结或底部结。取决于存储器元件是经历正向FORM还是反向FORM，底部或顶部结可以具有通道扩展。这在需要时提供了高压接点。

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