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51. 发明授权

US09497864B2 Circuit substrate, semiconductor package and process for fabricating the same 有权
标题翻译：电路基板，半导体封装及其制造方法
公开(公告)号：US09497864B2
公开(公告)日：2016-11-15
申请号：US13898486
申请日：2013-05-21
申请人： VIA Technologies, Inc.
发明人： Chen-Yueh Kung
IPC分类号： H05K1/18 , H05K1/11 , H05K3/40 , H05K3/00 , H01L23/13 , H01L23/367 , H01L23/498 , H05K3/28
CPC分类号： H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/4882 , H01L21/563 , H01L23/13 , H01L23/3185 , H01L23/3675 , H01L23/3677 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L2224/10 , H01L2224/16157 , H01L2224/73204 , H05K1/112 , H05K1/119 , H05K1/181 , H05K3/0026 , H05K3/28 , H05K3/4007 , H05K2201/09472 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H05K2203/0723 , H05K2203/107 , H05K2203/1476 , Y10T29/49156
摘要： A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.
摘要翻译：电路基板具有以下元件。层叠电路结构具有与其相对的第一表面和第二表面。第一图案化内导电层设置在第一表面上并具有多个焊盘。第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

52. 发明授权

US09466295B2 Method for correcting a speech response and natural language dialogue system 有权
标题翻译：纠正语音响应和自然语言对话系统的方法
公开(公告)号：US09466295B2
公开(公告)日：2016-10-11
申请号：US14142932
申请日：2013-12-30
申请人： VIA Technologies, Inc.
发明人： Guo-Feng Zhang
IPC分类号： G10L15/22 , G10L15/08 , G10L15/18
CPC分类号： G10L15/22 , G10L15/1822 , G10L2015/088
摘要： A natural language dialog system and a method capable of correcting a speech response are provided. The method includes following steps. A first speech input is received. At least one keyword included in the first speech input is parsed to obtain a candidate list having at least one report answers. One of the report answers is selected from the candidate list as a first report answer, and a first speech response is output according to the first report answer. A second speech input is received and parsed to determine whether the first report answer is correct. If the first report answer is incorrect, another report answer other than the first report answer is selected from the candidate list as a second report answer. According to the second report answer, a second speech response is output.
摘要翻译：提供了一种自然语言对话系统和能够校正语音响应的方法。该方法包括以下步骤。接收到第一个语音输入。解析包含在第一语音输入中的至少一个关键字以获得具有至少一个报告答案的候选列表。从候选列表中选择报告答案之一作为第一报告答案，并且根据第一报告答案输出第一语音响应。接收并解析第二个语音输入，以确定第一个报告答案是否正确。如果第一个报告答案不正确，则从候选人名单中选出除第一个报告答复之外的其他报告回答作为第二个报告答案。根据第二报告答案，输出第二个语音响应。

53. 发明授权

US09450580B2 Digital power gating with programmable control parameter 有权
标题翻译：具有可编程控制参数的数字电源门控
公开(公告)号：US09450580B2
公开(公告)日：2016-09-20
申请号：US14202313
申请日：2014-03-10
申请人： VIA TECHNOLOGIES, INC.
发明人： James R. Lundberg
IPC分类号： G05F1/10 , H03K19/00
CPC分类号： H03K19/0008
摘要： An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.
摘要翻译：包括全局电源总线，门控电源总线，耦合到门控电源总线的功能电路，存储编程控制参数的可编程器件和数字电源门控系统的集成电路。数字电源门控系统包括门控设备和电源门控控制系统。每个选通装置耦合在全局和门控供电总线之间，并且每个具有控制终端。电源门控控制系统控制数字控制值以控制门控设备的激活。电源门控控制系统被配置为通过调整数字控制值来执行电力门控操作，以控制门控电源总线相对于全局电源总线的电压的电压。电源门控操作可以使用编程的控制参数进行调整。可编程器件可以是保险丝阵列或用编程控制参数编程的存储器。

54. 发明授权

US09444165B2 Pin arrangement and electronic assembly 有权
标题翻译：引脚布置和电子组装
公开(公告)号：US09444165B2
公开(公告)日：2016-09-13
申请号：US14551094
申请日：2014-11-24
申请人： VIA Technologies, Inc.
发明人： Sheng-Yuan Lee
IPC分类号： H01R12/00 , H01R12/77 , H05K1/02 , H05K1/14 , H01R13/6473 , H01R13/6471 , H05K1/11
CPC分类号： H01R12/771 , H01R13/6471 , H01R13/6473 , H05K1/025 , H05K1/117 , H05K1/118 , H05K1/147 , H05K2201/09781 , H05K2201/10189
摘要： A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.
摘要翻译：提供一种适于FPC连接器的插脚布置。引脚布置包括引脚通道。引脚通道包括一对接地引脚，一对差分引脚和至少一个未连接（NC）引脚。差分引脚位于一对接地引脚之间。所述至少一个NC销位于所述一对差动销之间，或位于所述一对接地引脚中的一个与所述一对接地引脚中的一个与其相邻的所述一对差动引脚之一中。通过在所述一对差动引脚之间和/或差分引脚和与其相邻的接地引脚之间增加至少一个NC引脚，所述一对差动引脚和/或差分引脚与接地引脚之间的距离因此增加了一对差分引脚的差分特性阻抗，以减少阻抗失配的影响。

55. 发明授权

US09367497B2 Reconfigurably designating master core for conditional output on sideband communication wires distinct from system bus 有权
标题翻译：可重构地指定与系统总线不同的边带通信线路上的条件输出的主核
公开(公告)号：US09367497B2
公开(公告)日：2016-06-14
申请号：US14522931
申请日：2014-10-24
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Stephan Gaskins
IPC分类号： G06F13/36 , G06F15/163 , G06F1/32 , G06F1/24 , G06F9/30 , G06F9/50 , G06F9/445 , G06F15/82 , G06F11/36 , G06F11/14
CPC分类号： G06F1/26 , G06F1/24 , G06F1/3243 , G06F1/3287 , G06F9/30076 , G06F9/30083 , G06F9/44505 , G06F9/5094 , G06F11/1423 , G06F11/3664 , G06F13/36 , G06F15/163 , G06F15/82 , Y02D10/14 , Y02D10/22
摘要： A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.
摘要翻译：一种用于动态重新配置多核微处理器的一个或多个核心的方法，所述多核微处理器包括多个核心和边带通信线路，其外部连接到连接到芯片组的系统总线，这有助于非系统总线核心间通信。为了构建基于边带的核心间通信的目的，至少一些核可操作以可重新配置地指定或不具有主凭证。该方法包括确定微处理器的核心的初始配置，该配置指定至少一个核心，但不将所有核心指定为主核心，并且根据修改的配置重新配置核心，该修改的配置删除主命名从最初如此指定的核心，并将主指定分配给最初未指定的核心。每个核心被配置为基于其指定或不存在作为主核心有条件地驱动其所连接的边带通信线。

56. 发明申请

US20160162017A1 CENTRALIZED SYNCHRONIZATION MECHANISM FOR A MULTI-CORE PROCESSOR 有权
标题翻译：用于多核处理器的集中式同步机制
公开(公告)号：US20160162017A1
公开(公告)日：2016-06-09
申请号：US14994544
申请日：2016-01-13
申请人： VIA TECHNOLOGIES, INC.
发明人： G. GLENN HENRY , TERRY PARKS
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3287 , G06F1/04 , G06F1/32 , G06F9/522 , G06F12/0891 , G06F2212/1028 , G06F2212/60
摘要： A multi-core microprocessor supports a plurality of operating states that provide different levels of performance and power consumption to the microprocessor and its cores. A control unit puts selected cores into selected operating states at selected times. A core-specific synchronization register is provided for each core external to the core and readable by the control unit. Each core responds to an instruction to target an operating state by writing a value identifying the target operating state to the synchronization register. The control unit causes power saving actions that affect shared resources provided that the actions do not reduce performance of any core sharing the resources below the core's target operating state.
摘要翻译：多核微处理器支持向微处理器及其核心提供不同级别的性能和功耗的多个操作状态。控制单元在所选择的时间将选定的磁芯置于选定的运行状态。为核心外部的每个核心提供核心特定同步寄存器，并由控制单元读取。每个核心通过将标识目标操作状态的值写入同步寄存器来响应指令以对准操作状态的指令。如果行为不降低任何核心共享低于核心目标操作状态的资源的核心，控制单元就会产生影响共享资源的省电动作。

57. 发明授权

US09329995B2 Memory device and operating method thereof 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US09329995B2
公开(公告)日：2016-05-03
申请号：US14548549
申请日：2014-11-20
申请人： VIA TECHNOLOGIES, INC.
发明人： Liang Chen , Chen Xiu
IPC分类号： G06F12/02 , G06F11/14
CPC分类号： G06F12/0246 , G06F11/1441 , G06F2212/7201 , Y02D10/13
摘要： The invention provides a memory device. The memory device includes a flash memory, a memory, and a controller. The flash memory includes a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a specific requirement, and when the data access fulfills the conditions of the specific requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.
摘要翻译：本发明提供一种存储装置。存储器件包括闪存，存储器和控制器。闪存包括用于数据存储的多个块。存储器存储记录其中的块的逻辑地址和物理地址之间的关系的地址映射表。控制器将存储在存储器中的地址映射表分成多个映射表单元，更新存储在映射表单元中的逻辑地址和物理地址之间的关系，确定对闪速存储器执行的数据访问是否满足条件特定要求，并且当数据访问满足特定要求的条件时，控制器从映射表单元中选择目标映射表单元，并将目标映射表单元和对应的时间戳作为映射表单元数据存储到闪存

58. 发明授权

US09292470B2 Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program 有权
标题翻译：允许ARM ISA程序访问由x86 ISA程序编写的64位通用寄存器的微处理器
公开(公告)号：US09292470B2
公开(公告)日：2016-03-22
申请号：US13874878
申请日：2013-05-01
申请人： VIA Technologies, Inc.
发明人： Mark John Ebersole
IPC分类号： G06F9/22 , G06F15/78 , G06F9/30 , G06F9/44
CPC分类号： G06F15/7842 , G06F9/30076 , G06F9/30112 , G06F9/30138 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/4401
摘要： A microprocessor includes hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. The microprocessor also includes hardware registers that instantiate the ARM Architecture GPRs. In response to an ARM MRRC instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate two of the ARM GPRs registers. In response to an ARM MCRR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate two of the ARM Architecture GPRs registers. The hardware registers may be shared by the two Architectures.
摘要翻译：微处理器包括实例化Intel 64架构R8-R15 GPR的硬件寄存器。微处理器与每个R8-R15 GPR相关联，分别有独特的MSR地址。微处理器还包括实例化ARM架构GPR的硬件寄存器。为了响应指定R8-R15 GPR之一的相应唯一MSR地址的ARM MRRC指令，微处理器读取硬件寄存器中将指定的一个R8-R15 GPR实例化为硬件寄存器的内容，该硬件寄存器实例化为二的ARM GPR寄存器。为了响应指定R8-R15 GPR之一的相应唯一MSR地址的ARM MCRR指令，微处理器写入硬件寄存器，将R8-R15 GPR中指定的一个实例化为硬件寄存器的内容，实例化了两个的ARM架构GPR寄存器。硬件寄存器可能由两个架构共享。

59. 发明授权

US09274577B2 Adaptive USB charging method and system 有权
标题翻译：自适应USB充电方式和系统
公开(公告)号：US09274577B2
公开(公告)日：2016-03-01
申请号：US14490046
申请日：2014-09-18
申请人： VIA Technologies, Inc.
发明人： Yi-Lin Lai , Bo-Ming Huang , Kuo-Yu Wu
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/263 , G06F1/266 , G06F1/3212
摘要： An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.
摘要翻译：公开了一种自适应通用串行总线（USB）充电方法和系统。在低功耗状态下，USB设备以非USB充电模式进行充电。当不检测到耦合到USB设备的数据信号的变化时，保持非USB充电模式。当数据信号具有第一周期的变化时，它被切换到第三专有充电模式。

60. 发明授权

US09256554B2 Progress recording method and recovering method for encoding operation on storage device 有权
标题翻译：存储装置编码操作的进度记录方法和恢复方法
公开(公告)号：US09256554B2
公开(公告)日：2016-02-09
申请号：US13736092
申请日：2013-01-08
申请人： VIA Technologies, Inc.
发明人： Shou-Di Li , Guang-Hui Wu , Hai-Bin Shen
IPC分类号： G06F12/00 , G06F12/16 , G06F11/14
CPC分类号： G06F11/1438 , G06F11/1402 , G06F11/1441 , G06F12/16 , G06F2201/805 , G06F2201/85
摘要： A progress recording method and a corresponding recovering method adapted to an encoding operation performed on a storage area of a storage device are provided. The progress recording method includes the following steps. A variable set is initialized and stored. The encoding operation includes a plurality of sub-operations, and each of the sub-operations is corresponding to at least one flag variable in the variable set. The flag variables are used for recording execution progresses of the sub-operations. When each of the sub-operations is executed, the corresponding flag variable in the variable set is updated according to the execution progress of the sub-operation.
摘要翻译：提供了一种适用于对存储装置的存储区域执行的编码操作的进度记录方法和相应的恢复方法。进度记录方法包括以下步骤。初始化并存储变量集。编码操作包括多个子操作，并且每个子操作对应于变量集合中的至少一个标志变量。标志变量用于记录子操作的执行进度。当执行每个子操作时，根据子操作的执行进度来更新变量集中的相应标志变量。

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