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51. 发明申请

US20180234355A1 DATA-PLANE STATEFUL PROCESSING UNITS IN PACKET PROCESSING PIPELINES 审中-公开
公开(公告)号：US20180234355A1
公开(公告)日：2018-08-16
申请号：US15888050
申请日：2018-02-04
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Patrick Bosshart , Jay Evan Scott Peterson , Michael Gregory Ferrara , Steven Licking , Chaitanya Kodeboyina
IPC分类号： H04L12/931 , H04L12/00 , H04L12/26
CPC分类号： H04L49/00 , H04L12/00 , H04L43/0864
摘要： A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

52. 发明授权

US09923816B2 Data-plane stateful processing units in packet processing pipelines 有权
公开(公告)号：US09923816B2
公开(公告)日：2018-03-20
申请号：US14864032
申请日：2015-09-24
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Steven Licking , Anirudh Sivaraman Kaushalram , Chaitanya Kodeboyina
IPC分类号： H04L12/741 , H04L29/06
CPC分类号： H04L45/74 , H04L69/22
摘要： A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

53. 发明授权

US11606318B2 Messaging between remote controller and forwarding element 有权
公开(公告)号：US11606318B2
公开(公告)日：2023-03-14
申请号：US17867508
申请日：2022-07-18
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Xiaozhou Li , Anurag Agrawal , Julianne Zhu
IPC分类号： H04L49/90 , H03M13/09 , H04L45/7453 , H04L41/08 , H04L41/0803 , H04L49/00 , H04L49/10 , H04L69/22 , H04L41/06 , H04L49/101 , H04L49/20 , H04L9/40
摘要： Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

54. 发明授权

US11503141B1 Stateful processing unit with min/max capability 有权
公开(公告)号：US11503141B1
公开(公告)日：2022-11-15
申请号：US15835247
申请日：2017-12-07
申请人： Barefoot Networks, Inc.
发明人： Jay Evan Scott Peterson , Michael Gregory Ferrara , Patrick Bosshart , Changhoon Kim , Remy Chang
IPC分类号： H04L29/06 , H04L69/22 , H04L49/90 , H04L47/62 , H04L45/745
摘要： Some embodiments provide a network forwarding integrated circuit (IC) that includes at least one packet processing pipeline. The packet processing pipeline includes multiple match-action stages, at least one of which includes a stateful processing unit that operates at a line rate of the network forwarding IC. The stateful processing unit is configured to receive data stored in a memory location associated with a stateful table of the match-action stage. The data includes a set of values. The stateful processing unit is further configured to identify one of a maximum value and a minimum value from the set of values, and to output the identified value for use by a next match-action stage.

55. 发明授权

US11463381B2 Network forwarding element with key-value processing in the data plane 有权
公开(公告)号：US11463381B2
公开(公告)日：2022-10-04
申请号：US17092136
申请日：2020-11-06
申请人： Barefoot Networks, Inc.
发明人： Xiaozhou Li , Jeongkeun Lee , Changhoon Kim , John Nathan Foster
IPC分类号： H04L49/00 , H04L45/00 , H04L45/74 , G06F3/06 , H04L45/745
摘要： Some embodiments of the invention provide a forwarding element (e.g., a switch, a router, etc.) that has one or more data plane, message-processing pipelines with key-value processing circuits. The forwarding element's data plane key-value circuits allow the forwarding element to perform key-value services that would otherwise have to be performed by data compute nodes connected by the network fabric that includes the forwarding element. In some embodiments, the key-value (KV) services of the forwarding element and other similar forwarding elements supplement the key-value services of a distributed set of key-value servers by caching a subset of the most commonly used key-value pairs in the forwarding elements that connect the set of key-value servers with their client applications. In some embodiments, the key-value circuits of the forwarding element perform the key-value service operations at message-processing line rates at which the forwarding element forwards messages to the data compute nodes and/or to other network forwarding elements in the network fabric.

56. 发明授权

US11444889B2 Forwarding element data plane with computing parameter distributor 有权
公开(公告)号：US11444889B2
公开(公告)日：2022-09-13
申请号：US17255984
申请日：2019-03-08
申请人： Barefoot Networks, Inc.
发明人： Masoud Moshref Javadi , Changhoon Kim , Patrick W. Bosshart , Anurag Agrawal
IPC分类号： H04L12/935 , H04L49/00 , G06F9/455 , G06N3/08
摘要： Some embodiments provide a network forwarding element with a data-plane forwarding circuit that has a parameter collecting circuit to store and distribute parameter values computed by several machines in a network. In some embodiments, the machines perform distributed computing operations, and the parameter values that compute are parameter values associated with the distributed computing operations. The parameter collecting circuit of the data-plane forwarding circuit (data plane) in some embodiments (1) stores a set of parameter values computed and sent by a first set of machines, and (2) distributes the collected parameter values to a second set of machines once it has collected the set of parameter values from all the machines in the first set. The first and second sets of machines are the same set of machines in some embodiments, while they are different sets of machines (e.g., one set has at least one machine that is not in the other set) in other embodiments. In some embodiments, the parameter collecting circuit performs computations on the parameter values that it collects and distributes the result of the computations once it has processed all the parameter values distributed by the first set of machines. The computations are aggregating operations (e.g., adding, averaging, etc.) that combine corresponding subset of parameter values distributed by the first set of machines.

57. 发明授权

US11134032B1 Augmenting data plane functionality with field programmable integrated circuits 有权
公开(公告)号：US11134032B1
公开(公告)日：2021-09-28
申请号：US16540750
申请日：2019-08-14
申请人： Barefoot Networks, Inc.
发明人： Antonin Mathieu Bas , Anurag Agrawal , Changhoon Kim
IPC分类号： H04L12/879
摘要： Some embodiments use one or more FPGAs and external memories associated with the FPGAs to implement large, hash-addressable tables for a data plane circuit. These embodiments configure at least one message processing stage of the DP circuit to store (1) a first plurality of records for matching with a set of data messages received by the DP circuit, and (2) a redirection record redirecting data messages that do not match the first plurality of records to a DP egress port associated with the memory circuit. These embodiments configure an external memory circuit to store a larger, second set of records for matching with redirected data messages received through the DP egress port associated with the memory circuit. This external memory circuit is a hash-addressable memory in some embodiments. To determine whether a redirected data message matches a record in the second set of record, the method of some embodiments configures an FPGA associated with the hash-addressable external memory to use a collision free hash process to generate a collision-free, hash address value from a set of attributes of the data message. This hash address value specifies an address in the external memory for the record in the second set of records to compare with the redirected data message.

58. 发明授权

US10819633B2 Data-plane stateful processing units in packet processing pipelines 有权
公开(公告)号：US10819633B2
公开(公告)日：2020-10-27
申请号：US15888054
申请日：2018-02-04
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Steven Licking , Anirudh Sivaraman Kaushalram , Chaitanya Kodeboyina
IPC分类号： H04L12/741 , H04L29/06
摘要： A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

59. 发明授权

US10700959B2 Source routing design with simplified forwarding elements 有权
公开(公告)号：US10700959B2
公开(公告)日：2020-06-30
申请号：US15948946
申请日：2018-04-09
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Jeongkeun Lee , Milad Sharif , Robert Soule
IPC分类号： H04L12/751 , H04L12/721 , H04L12/24 , H04L12/741 , H04L12/26 , H04L29/06 , H04L12/773 , H04L9/06
摘要： Some embodiments provide a network that includes (i) multiple forwarding elements, (ii) a set of one or more global control plane (GCP) servers, and (iii) multiple end-node machines. The GCP servers maintain topological information about connections between the forwarding elements. Each of the end-node machines receives the topological information, identifies a source-routing path for a message sent by the machine, and embeds the source-routing path in a source-routing message header that includes an egress port for each forwarding element along the path.

60. 发明授权

US10608939B1 Identifying congestion in a network 有权
公开(公告)号：US10608939B1
公开(公告)日：2020-03-31
申请号：US15895908
申请日：2018-02-13
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Jeongkeun Lee , Xiaozhou Li , Masoud Moshref Javadi , Georgios Nikolaidis , Ethan M. Spiegel
IPC分类号： H04L12/741 , H04L12/801 , H04L12/933 , H04L12/26 , H04L12/863
摘要： Some embodiments of the invention provide a method for reporting congestion in a network that includes several forwarding elements. In a data plane circuit of one of the forwarding elements, the method detects that a queue in the switching circuit of the data plane circuit is congested, while a particular data message is stored in the queue as it is being processed through the data plane circuit. In the data plane circuit, the method then generates a report regarding the detected queue congestion, and sends this report to a data collector external to the forwarding element. To send the report, the data plane circuit in some embodiments duplicates the particular data message, stores it in the duplicate data message information regarding the detected queue congestion, and sends the duplicate data message to the external data collector.

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