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51. 发明申请

US20110298440A1 LOW VOLTAGE SIGNALING 有权
标题翻译：低电压信号
公开(公告)号：US20110298440A1
公开(公告)日：2011-12-08
申请号：US12794995
申请日：2010-06-07
申请人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
发明人： Leland Chang , Robert H. Dennard , Brian L. Ji , Wing K. Luk , Robert K. Montoye
IPC分类号： G05F5/00
CPC分类号： H02M3/07 , H02M2003/072
摘要： A low voltage signaling system for integrated circuits includes a first voltage domain operating at a nominal integrated circuit (IC) power supply voltage (Vdd) swing level at a signal transmitting end of a first chip, a second voltage domain having one or more transmission interconnect lines operating at a reduced voltage swing level with respect to the first voltage domain, and a third voltage domain at a signal receiving end of a second chip, the third voltage domain operating at the Vdd swing level; wherein an input signal originating from the first voltage domain is down converted to operate at the reduced voltage swing level for transmission over the second voltage domain, and wherein the third voltage domain senses the input signal transmitted over the second voltage domain and generates an output signal operating back up at the Vdd swing level.
摘要翻译：用于集成电路的低电压信号系统包括在第一芯片的信号发射端处以标称集成电路（IC）电源电压（Vdd）摆幅电平操作的第一电压域，具有一个或多个传输互连的第二电压域以相对于第一电压域的降低的电压摆动电平工作的线路，以及在第二芯片的信号接收端的第三电压域，以Vdd摆动电平工作的第三电压域; 其中源自所述第一电压域的输入信号被降频转换以在所述降低的电压摆幅电平下工作以在所述第二电压域上传输，并且其中所述第三电压域检测在所述第二电压域上传输的输入信号，并产生输出信号以Vdd摆动水平运行。

52. 发明申请

US20110115021A1 ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX 有权
标题翻译：具有超薄SOI和ULTRATHIN BOX的SOI器件的隔离结构
公开(公告)号：US20110115021A1
公开(公告)日：2011-05-19
申请号：US12618871
申请日：2009-11-16
申请人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , Marwan H. Khater , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L29/786 , H01L29/06 , H01L21/762
CPC分类号： H01L21/76264 , H01L21/76232
摘要： Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.
摘要翻译：浅埋沟形成在埋入绝缘体部分和顶部半导体部分的垂直堆叠周围。介电材料层直接沉积在顶部半导体部分的侧壁上。通过用诸如氧化硅的介电材料填充浅沟槽来形成浅沟槽隔离结构。在平坦化之后，顶部半导体部分被电介质材料层横向接触并包围。介电材料层防止在湿蚀刻期间在掩埋绝缘体部分下面的手柄基板的暴露，从而确保手柄基板和随后形成在顶部半导体部分上的栅电极之间的电隔离。

53. 发明申请

US20100176482A1 LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION 审中-公开
标题翻译：具有后续自对准的双盒背盖的低成本制造硅绝缘体波纹
公开(公告)号：US20100176482A1
公开(公告)日：2010-07-15
申请号：US12352077
申请日：2009-01-12
申请人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
发明人： Robert H. Dennard , David R. Greenberg , Amlan Majumdar , Leathen Shi , Jeng-Bang Yau
IPC分类号： H01L27/12 , H01L21/762 , H01L29/06
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/76275 , H01L21/76283 , H01L27/1203
摘要： A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.
摘要翻译：用于制造集成电路器件的半导体衬底结构包括块状衬底; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在下绝缘层上的导电层; 在所述导电层上形成具有蚀刻停止特性的绝缘体; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。还公开了一种随后构建双深度浅沟槽隔离的方案，其中在与这种半导体衬底中的有源区域中较浅的STI自对准的背栅层中的较深STI相比较。

54. 发明申请

US20090285018A1 Gated Diode Memory Cells 有权
标题翻译：门控二极管存储单元
公开(公告)号：US20090285018A1
公开(公告)日：2009-11-19
申请号：US12512559
申请日：2009-07-30
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： G11C11/36 , G11C7/00
CPC分类号： G11C11/405
摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).
摘要翻译：提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（“FET”），以及与FET信号通信的门控二极管，使得门控二极管的栅极与源极信号通信第一FET的栅极，其中栅极二极管的栅极形成存储单元的一个端子，并且门控二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（“BL” “），并且第一FET的栅极与写入字线（”WLw“）进行信号通信，并且门控二极管的源极与读取字线（”WLr“）进行信号通信。

55. 发明授权

US07358166B2 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US07358166B2
公开(公告)日：2008-04-15
申请号：US11208359
申请日：2005-08-19
申请人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L21/205 , H01L21/477
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

56. 发明授权

US07242629B2 High speed latch circuits using gated diodes 有权
标题翻译：使用门控二极管的高速锁存电路
公开(公告)号：US07242629B2
公开(公告)日：2007-07-10
申请号：US11491701
申请日：2006-07-24
申请人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
发明人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
IPC分类号： G11C7/00 , G11C7/02 , G01R19/00 , H03F3/60
CPC分类号： G11C7/065 , G11C7/06 , H03F1/56 , H03F3/10 , H03F3/347 , H03F2200/183
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
摘要翻译：读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

57. 发明授权

US07180814B2 Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture 有权
标题翻译：具有小电压摆幅传输，电压再生和宽带宽架构的低功率电路
公开(公告)号：US07180814B2
公开(公告)日：2007-02-20
申请号：US11248863
申请日：2005-10-12
申请人： Wing K. Luk , Robert H. Dennard , Stephen V. Kosonocky
发明人： Wing K. Luk , Robert H. Dennard , Stephen V. Kosonocky
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C11/406 , G11C11/4074 , G11C2207/104
摘要： An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.
摘要翻译：诸如存储器宏的集成电路包括支持第一和第二电压差的多个电源轨，第二电压差小于第一电压差。集成电路中的信号线由小的摆动电路产生的小电压摆动驱动。集成电路还包括正在接收小电压摆幅输入并且正在输出第一或全电压摆幅的再生电路。将小电压摆幅应用于信号线节省了集成电路中的功率。宽带宽全字I / O存储器集成电路在连接到同一字线和对应的I / O端子的基本上所有的存储器单元之间具有同时可操作的连接路径，并且具有单端数据线结构。

58. 发明授权

US07106620B2 Memory cell having improved read stability 有权
标题翻译：具有改善的读稳定性的存储单元
公开(公告)号：US07106620B2
公开(公告)日：2006-09-12
申请号：US11069018
申请日：2005-02-28
申请人： Leland Chang , Robert H. Dennard , Robert Kevin Montoye
发明人： Leland Chang , Robert H. Dennard , Robert Kevin Montoye
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , H01L27/11 , H01L27/1104
摘要： A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell. The read circuit includes a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array. The read circuit is configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit. The memory cell is configured such that the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the first write bit line during the read operation. A strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in the write circuit and/or the read circuit.
摘要翻译：用于存储器阵列的存储单元包括用于存储存储单元的逻辑状态的存储元件，写入电路和读取电路。写入电路用于响应于用于选择性地写入存储器单元的逻辑状态的写入信号，有选择地将存储元件的第一节点连接到存储器阵列中的至少第一写入位线。读取电路包括连接到存储元件的基本上高阻抗的输入节点和可连接到存储器阵列的读取位线的输出节点。读取电路被配置为响应于施加到读取电路的读取信号而在输出节点处产生代表存储元件的逻辑状态的输出信号。存储单元被配置为使得在存储单元的读取操作期间禁止写入电路，以便在读取操作期间基本上将存储元件与第一写入位线隔离。存储元件中的至少一个晶体管器件的强度相对于写入电路和/或读取电路中的至少一个晶体管器件的强度分别优化。

59. 发明授权

US07099216B2 Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing 失效
标题翻译：单周期读/写/写回流水线，全字字I / O DRAM架构，具有增强的写和单端感测功能
公开(公告)号：US07099216B2
公开(公告)日：2006-08-29
申请号：US10656596
申请日：2003-09-05
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C7/067 , G11C11/4091 , G11C2207/104
摘要： A DRAM is disclosed which includes a single ended bitline structure, a single ended global bitline structure, primary sense amplifiers with data storage and data write-back capability and with capability to decouple from the global bitlines, a full-wordline I/O structure where essentially all memory cell that belong to the same wordline are being operated on, and a pipelined architecture. The DRAM further includes a small voltage swing design. The primary sense amplifiers can include more than one amplification stages. Such a DRAM is suitable for applications in conjunction with processors as an embedded DRAM.
摘要翻译：公开了一种DRAM，其包括单端位线结构，单端全局位线结构，具有数据存储和数据回写能力的初级读出放大器，以及具有与全局位线分离的能力的全字I / O结构，其中基本上所有属于相同字线的所有存储器单元正在被操作，以及流水线架构。 DRAM还包括小电压摆幅设计。主感测放大器可以包括多于一个的放大级。这样的DRAM适用于作为嵌入式DRAM的处理器的应用。

60. 发明授权

US5206544A CMOS off-chip driver with reduced signal swing and reduced power supply disturbance 失效
标题翻译： CMOS片外驱动器具有降低的信号摆幅和减少电源干扰
公开(公告)号：US5206544A
公开(公告)日：1993-04-27
申请号：US682753
申请日：1991-04-08
申请人： Chih-Liang Chen , Robert H. Dennard , Hussein I. Hanafi
发明人： Chih-Liang Chen , Robert H. Dennard , Hussein I. Hanafi
IPC分类号： H03K17/00 , H03K17/16 , H03K17/687 , H03K19/0175
CPC分类号： H03K17/163 , H03K2217/0036
摘要： An off-chip driver circuit which includes a complementary pair of field effect transistor source followers connected in a non-inverting series circuit arrangement. The driver circuit includes an n-channel device to pull the output up to the positive supply less the threshold drop across the device and a p-channel device to pull the output down for the opposite transition to within a threshold voltage drop above ground of the p-channel device. The driver circuit includes means for eliminating body effect by connecting the n(p)-well of the p(n) channel transistor to the output node. The driver circuit provides a reduced swing low noise output which reduces the collapse of the power supply. The driver circuit provides an appropriate impedance match to the output transmission line, so that the output transmission line can be terminated to eliminate reflections.
摘要翻译：片外驱动电路，其包括以非反相串联电路布置连接的互补的一对场效应晶体管源极跟随器。驱动器电路包括n沟道器件，用于将输出拉至正电源，减去器件上的阈值下降，以及p沟道器件，以将输出向下拉，用于相反的转变，使之达到在 p通道设备。驱动器电路包括通过将p（n）沟道晶体管的n（p）阱连接到输出节点来消除体效应的装置。驱动器电路提供降低的摆幅低噪声输出，减少电源的崩溃。驱动电路为输出传输线提供适当的阻抗匹配，从而可以终止输出传输线，以消除反射。

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