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51. 发明申请

US20090026585A1 Semiconductor Device and Method for Manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090026585A1
公开(公告)日：2009-01-29
申请号：US12209399
申请日：2008-09-12
申请人： Seok Su Kim
发明人： Seok Su Kim
IPC分类号： H01L23/544
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device consistent with the present invention includes a semiconductor substrate having a semiconductor chip region and a scribe region; a first insulating layer formed in the semiconductor chip region of the semiconductor substrate; a metal contact plug formed in the first insulating layer; a metal sidewall formed on a side of the first insulating layer in the scribe region; a metallization wiring electrically connected with the substrate via the metal contact plug; and a second insulating layer and a protective layer formed over the metal contact plug and the metal sidewall so as to cover the semiconductor chip region and the scribe region.
摘要翻译：符合本发明的半导体器件包括具有半导体芯片区域和划线区域的半导体衬底; 形成在半导体衬底的半导体芯片区域中的第一绝缘层; 形成在所述第一绝缘层中的金属接触插塞; 形成在划线区域中的第一绝缘层侧的金属侧壁; 通过所述金属接触插塞与所述基板电连接的金属化布线; 以及形成在金属接触插塞和金属侧壁上的第二绝缘层和保护层，以覆盖半导体芯片区域和划线区域。

52. 发明授权

US07482692B2 Tungsten plug structure of semiconductor device and method for forming the same 有权
标题翻译：半导体器件的钨插头结构及其形成方法
公开(公告)号：US07482692B2
公开(公告)日：2009-01-27
申请号：US11320698
申请日：2005-12-30
申请人： In Kyu Chun
发明人： In Kyu Chun
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A tungsten plug structure of a semiconductor device wherein a method for forming the same is performed at least twice to form a tungsten plug having a low aspect ratio, thereby obtaining an overlap margin between the tungsten plug and a metal line and minimizing contact resistance between the tungsten plug and a lower metal line layer. The plug structure of a semiconductor device includes a silicon substrate in which various elements for the semiconductor device are formed, a first dielectric film formed on the silicon substrate, having a first contact hole, a first plug buried in the first contact hole of the first dielectric film, having a low aspect ratio, a second dielectric film formed on an entire surface including the first dielectric film, having a second contact hole on the first plug, a second plug buried in the second contact hole of the second dielectric film, having a low aspect ratio, and a metal line formed on the second plug.
摘要翻译：一种半导体器件的钨插头结构，其中形成其形成方法至少两次以形成具有低纵横比的钨插塞，由此获得钨插头和金属线之间的重叠余量，并使接触电阻最小化钨丝塞和下金属线层。半导体器件的插头结构包括其中形成用于半导体器件的各种元件的硅衬底，形成在硅衬底上的第一电介质膜，具有第一接触孔，第一插头埋入第一接触孔具有低纵横比的介电膜，在包括第一电介质膜的整个表面上形成的第二电介质膜，在第一插塞上具有第二接触孔，埋在第二电介质膜的第二接触孔中的第二电极，具有低纵横比，以及形成在第二插头上的金属线。

53. 发明授权

US07482276B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07482276B2
公开(公告)日：2009-01-27
申请号：US11613210
申请日：2006-12-20
申请人： Han Choon Lee , Kyung Min Park , Cheon Man Shim
发明人： Han Choon Lee , Kyung Min Park , Cheon Man Shim
IPC分类号： H01L21/311
CPC分类号： H01L21/76831 , H01L21/76825 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing same, capable of preventing the material of a barrier metal layer from penetrating into an intermetallic insulating layer are provided. In an embodiment, the device can include: a first metal interconnection formed in a lower insulating layer on a semiconductor substrate; an intermetallic insulating layer formed on the lower insulating layer including the first metal interconnection, the intermetallic insulating layer having a via hole and a trench for a second metal interconnection connecting to the first metal interconnection; a carbon implantation layer formed on inner walls of the via hole and the trench of the intermetallic insulating layer; a barrier metal layer deposited on the first metal interconnection exposed through the via hole and on the carbon implantation layer; a via formed in the via hole; and the second metal interconnection formed in the trench.
摘要翻译：提供了能够防止阻挡金属层的材料渗透到金属间绝缘层中的半导体器件及其制造方法。在一个实施例中，该器件可以包括：形成在半导体衬底上的下绝缘层中的第一金属互连; 形成在包括第一金属互连的下绝缘层上的金属间绝缘层，具有通孔的金属间绝缘层和连接到第一金属互连的第二金属互连的沟槽; 在所述通孔的内壁和所述金属间绝缘层的沟槽上形成的碳注入层; 沉积在通过通孔和碳注入层暴露的第一金属互连上的阻挡金属层; 通孔形成在通孔中; 以及形成在沟槽中的第二金属互连。

54. 发明授权

US07476592B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07476592B2
公开(公告)日：2009-01-13
申请号：US11646894
申请日：2006-12-27
申请人： Kee Joon Choi
发明人： Kee Joon Choi
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L29/78
摘要： A semiconductor device is provided. The semiconductor device according to the present invention includes a semiconductor substrate, a second insulation layer, a buffer insulation layer adjacent to the second insulation layer, a third insulation layer and transistors. A high voltage device region and a low voltage device region are defined in the semiconductor substrate. The second and third insulation layers are formed in the high and low voltage device regions, respectively. The transistors are formed on the second and third insulation layers, respectively.
摘要翻译：提供半导体器件。根据本发明的半导体器件包括半导体衬底，第二绝缘层，与第二绝缘层相邻的缓冲绝缘层，第三绝缘层和晶体管。在半导体衬底中限定高电压器件区域和低电压器件区域。第二和第三绝缘层分别形成在高电压和低电压器件区域中。晶体管分别形成在第二绝缘层和第三绝缘层上。

55. 发明授权

US07470596B2 Capacitors having a horizontally folded dielectric layer and methods for manufacturing the same 失效
标题翻译：具有水平折叠的电介质层的电容器及其制造方法
公开(公告)号：US07470596B2
公开(公告)日：2008-12-30
申请号：US11287675
申请日：2005-11-28
申请人： Hyuk Woo
发明人： Hyuk Woo
IPC分类号： H01L21/20
CPC分类号： H01L28/87 , H01L23/5223 , H01L27/0805 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： Capacitors having a horizontally folded dielectric layer and methods of manufacturing is the same are provided. An example method for manufacturing a capacitor includes forming a first insulating layer pattern above a substrate, forming a first silicon epitaxial growth layer above a region of the silicon substrate exposed by the first insulating layer pattern through epitaxial growth of a first silicon layer, selectively etching the first insulating layer pattern, forming a dielectric layer pattern above the lateral surface of the first silicon epitaxial growth layer in a shape of a spacer, and forming a second silicon epitaxial growth layer above the silicon substrate through epitaxial growth of a second silicon layer. A capacitor including electrodes made of the first and second silicon epitaxial growth layers with the dielectric layer pattern formed therebetween may be formed by such a method.
摘要翻译：具有水平折叠的介电层的电容器和制造方法是相同的。用于制造电容器的示例性方法包括在衬底上形成第一绝缘层图案，通过第一硅层的外延生长在由第一绝缘层图案暴露的硅衬底的区域之上形成第一硅外延生长层，选择性蚀刻第一绝缘层图案，在第一硅外延生长层的侧表面上方形成间隔物形状的电介质层图案，并通过第二硅层的外延生长在硅衬底之上形成第二硅外延生长层。可以通过这样的方法形成包括由第一和第二硅外延生长层制成的电极的电容器，其间形成介电层图案。

56. 发明授权

US07468319B2 Method for preventing a metal corrosion in a semiconductor device 失效
标题翻译：用于防止半导体器件中的金属腐蚀的方法
公开(公告)号：US07468319B2
公开(公告)日：2008-12-23
申请号：US11179455
申请日：2005-07-11
申请人： Jae Suk Lee
发明人： Jae Suk Lee
IPC分类号： H01L21/44
CPC分类号： H01L21/76888 , H01L21/02071 , H01L21/31138 , H01L21/32136
摘要： The present invention relates to a method for preventing a metal corrosion in a semiconductor device. The present method includes the steps of etching of a metal layer in a chamber, the metal layer having a photoresist pattern thereon or thereover; oxidizing a surface of the metal layer using a plasma comprising N2O in the same chamber; and removing the photoresist. Therefore, metal corrosion as well as bridges between metal wirings can be suppressed or prevented, thereby improving the profile of metal layer and the reliability and yield of the semiconductor device.
摘要翻译：本发明涉及一种在半导体器件中防止金属腐蚀的方法。本方法包括以下步骤：在室中蚀刻金属层，金属层在其上具有光致抗蚀剂图案; 在同一室中使用包含N 2 O的等离子体对金属层的表面进行氧化; 并去除光致抗蚀剂。因此，可以抑制或防止金属腐蚀以及金属布线之间的桥接，从而改善金属层的轮廓以及半导体器件的可靠性和产量。

57. 发明授权

US07465979B2 Semiconductor device and fabrication method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07465979B2
公开(公告)日：2008-12-16
申请号：US11644204
申请日：2006-12-22
申请人： Hyung Sun Yun
发明人： Hyung Sun Yun
IPC分类号： H01L29/94 , H01L21/8234
CPC分类号： H01L29/4232 , H01L21/823828 , H01L29/42372 , H01L29/7833 , H01L29/78648
摘要： In order to diversify a current control method of a semiconductor device, improve performance (including a current drive performance) of the semiconductor device, and reduce a size of the semiconductor device, a second gate may be formed inside a substrate that forms a channel upon applying a bias voltage thereto. In one aspect, the semiconductor device includes: a well region of a first conductivity; source and drain regions of a second conductivity in the well region; a first gate on an oxide layer above the well region, controlling a first channel region of a second conductivity between the source region and the drain region; and a second gate under the first channel region.
摘要翻译：为了使半导体器件的电流控制方法多样化，提高半导体器件的性能（包括电流驱动性能）并减小半导体器件的尺寸，可以在形成沟道的衬底内部形成第二栅极向其施加偏置电压。在一个方面，半导体器件包括：第一导电性的阱区; 在所述阱区中具有第二导电性的源区和漏区; 在阱区上方的氧化物层上的第一栅极，控制源区和漏区之间的第二导电性的第一沟道区; 以及在第一通道区域下方的第二栅极。

58. 发明授权

US07449387B2 MOS transistor and method of manufacturing the same 失效
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US07449387B2
公开(公告)日：2008-11-11
申请号：US11319595
申请日：2005-12-29
申请人： Yong Guen Lee
发明人： Yong Guen Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7833
摘要： A manufacturing method of a double LDD MOS transistor includes forming a gate electrode on a semiconductor substrate; forming a first LDD area by implanting and thermally annealing impurity ions using the gate electrode as a mask; forming a first spacer on both lateral walls of the gate electrode; forming a second LDD area by implanting and thermally annealing impurity ions using the gate electrode and the first spacer as a mask; forming a second spacer on both lateral walls of the gate electrode and the first spacer; and forming a source-drain diffusion area by implanting and thermally annealing impurity ions using the gate electrode, the first spacer, and the second spacer as a mask.
摘要翻译：双LDD MOS晶体管的制造方法包括在半导体衬底上形成栅电极; 通过使用所述栅极电极作为掩模注入和热退火杂质离子来形成第一LDD区域; 在栅电极的两个侧壁上形成第一间隔物; 通过使用所述栅极电极和所述第一间隔物作为掩模注入和热退火杂质离子来形成第二LDD区域; 在所述栅极电极和所述第一间隔物的两个侧壁上形成第二间隔物; 以及通过使用所述栅极电极，所述第一间隔物和所述第二间隔物作为掩模注入和热退火杂质离子来形成源极 - 漏极扩散区域。

59. 发明授权

US07442975B2 CMOS image sensor and method for fabricating the same 有权
标题翻译： CMOS图像传感器及其制造方法
公开(公告)号：US07442975B2
公开(公告)日：2008-10-28
申请号：US11319490
申请日：2005-12-29
申请人： Chang Eun Lee
发明人： Chang Eun Lee
IPC分类号： H01L31/113 , H01L21/00
CPC分类号： H01L27/14685 , H01L27/14627
摘要： A CMOS image sensor and a method for fabricating the same prevent a lifting effect of microlenses. Also, a diffused reflection of microlenses is prevented. The CMOS image sensor includes photodiodes, an interlayer insulating layer, metal lines formed in the interlayer insulating layer to electrically connect the respective photodiodes with each other, an oxide layer, a passivation layer to protect the CMOS image sensor from external sources, and microlenses formed to pass through the passivation layer at portions corresponding to the photodiodes.
摘要翻译： CMOS图像传感器及其制造方法防止微透镜的提升效果。此外，防止了微透镜的漫反射。 CMOS图像传感器包括光电二极管，层间绝缘层，形成在层间绝缘层中以将各个光电二极管彼此电连接的金属线，氧化物层，保护CMOS图像传感器免受外部源的钝化层和形成的微透镜在对应于光电二极管的部分处通过钝化层。

60. 发明授权

US07442639B2 Method of forming plug of semiconductor device 失效
标题翻译：形成半导体器件插头的方法
公开(公告)号：US07442639B2
公开(公告)日：2008-10-28
申请号：US11027408
申请日：2004-12-30
申请人： Han-Choon Lee , Jin-Woo Park
发明人： Han-Choon Lee , Jin-Woo Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838
摘要： A method for forming a plug of a semiconductor device according to a preferred embodiment includes forming a metal wiring on a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate having the metal wiring, forming a contact hole for partially exposing the metal wiring by selectively etching the interlayer dielectric layer, annealing the semiconductor substrate having the contact hole using NH3 gas, plasma processing the annealed semiconductor substrate using the NH3, and forming a barrier layer on the interlayer dielectric layer having the contact hole.
摘要翻译：根据优选实施例的形成半导体器件的插头的方法包括在半导体衬底上形成金属布线，在具有金属布线的半导体衬底上形成层间电介质层，形成用于部分地暴露金属布线的接触孔选择性地蚀刻层间电介质层，使用NH 3气体退火具有接触孔的半导体衬底，使用NH 3等离子体处理退火的半导体衬底，以及形成阻挡层在具有接触孔的层间绝缘层上。

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