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51. 发明申请

US20160163393A1 PARTIAL BLOCK ERASE FOR DATA REFRESHING AND OPEN-BLOCK PROGRAMMING 有权
标题翻译：数据刷新和开放编程的部分块删除
公开(公告)号：US20160163393A1
公开(公告)日：2016-06-09
申请号：US14863584
申请日：2015-09-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： Guirong Liang , Zhenming Zhou , Masaaki Higashitani
IPC分类号： G11C16/14 , G11C16/34 , G11C16/26
CPC分类号： G06F11/1068 , G06F11/1048 , G11C5/063 , G11C11/5628 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C2211/5644 , H01L27/11524
摘要： Systems and methods for performing partial block erase operations on a subset of word lines within a memory array prior to performing data refreshing or open-block programming are described. In some cases, data stored in memory cells connected to a word line with a fail bit count above an error threshold (e.g., more than two bit errors per page or more than three bit errors per word line) may be refreshed by performing a read operation on the memory cells, generating corrected data for the memory cells, performing a partial block erase operation on one or more word lines including the word line, and then writing the corrected data into the memory cells. The one or more word lines may include the word line with the fail bit count above the error threshold and an adjacent word line that is adjacent to the word line.
摘要翻译：描述了在执行数据刷新或开放块编程之前在存储器阵列内的字线子集上执行部分块擦除操作的系统和方法。在一些情况下，可以通过执行读取来刷新存储在具有错误位计数高于误差阈值的字线的存储器单元中的数据（例如，每页多于两个位错误或每个字线多于三个位错误）对存储器单元进行操作，产生用于存储单元的校正数据，对包括字线的一条或多条字线执行部分块擦除操作，然后将校正数据写入存储单元。一个或多个字线可以包括具有高于误差阈值的故障位计数的字线和与字线相邻的相邻字线。

52. 发明授权

US09361991B1 Efficient scanning of nonvolatile memory blocks 有权
标题翻译：非易失性存储块的高效扫描
公开(公告)号：US09361991B1
公开(公告)日：2016-06-07
申请号：US14581748
申请日：2014-12-23
申请人： SanDisk Technologies, Inc.
发明人： Yew Yin Ng , Gautam Dusija , Dennis S. Ea , Mrinal Kochar
IPC分类号： G11C16/04 , G11C16/26 , G11C11/56
CPC分类号： G11C11/5628 , G11C8/12 , G11C15/046 , G11C16/0483 , G11C16/08 , G11C2211/5648
摘要： A method of searching for a boundary between a written portion and an unwritten portion of an open block may include performing a word line by word line binary search of a first physical area of the open block to identify a last written word line of the first physical area of the block, and subsequently, searching in at least a second physical area of the open block based on the last written word line of the first physical area of the block as identified by the binary search.
摘要翻译：搜索开放块的写入部分和未写入部分之间的边界的方法可以包括通过开放块的第一物理区域的字线二进制搜索来执行字线，以识别第一物理的最后写入字线区域，并且随后，基于通过二叉搜索识别的块的第一物理区域的最后写入字线，在开放块的至少第二物理区域中进行搜索。

53. 发明授权

US09355713B2 Systems and methods for lower page writes 有权
标题翻译：较低页面写入的系统和方法
公开(公告)号：US09355713B2
公开(公告)日：2016-05-31
申请号：US14528892
申请日：2014-10-30
申请人： SanDisk Technologies Inc.
发明人： Jianmin Huang , Bo Lei , Jun Wan , Gerrit Jan Hemink , Steven T. Sprouse , Dana Lee
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C2211/5641
摘要： In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.
摘要翻译：在多级单元（MLC）存储器阵列块中，首先写入低层页面，在任何高层页面之前，下层数据进行异或（XOR）操作，以便如果任何下层页面由ECC（UECC）无法校正），则可以使用XOR恢复页面。这些块中的下页可以以非顺序的顺序写入。

54. 发明申请

US20160149004A1 3D NAND With Oxide Semiconductor Channel 有权
标题翻译： 3D NAND与氧化物半导体通道
公开(公告)号：US20160149004A1
公开(公告)日：2016-05-26
申请号：US14552964
申请日：2014-11-25
申请人： SanDisk Technologies Inc.
发明人： Peter Rabkin , Johann Alsmeier , Masaaki Higashitani
IPC分类号： H01L29/24 , H01L29/423 , H01L27/115
CPC分类号： H01L29/24 , H01L21/02565 , H01L21/02631 , H01L21/28282 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/4234 , H01L29/66969 , H01L29/7869 , H01L29/7926
摘要： Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline structure may have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc.
摘要翻译：这里公开了具有氧化物半导体垂直NAND通道的3D NAND存储器件及其形成方法。氧化物半导体可以具有晶体结构。垂直取向的NAND串的通道可以是圆柱形的。晶体结构具有一个轴线，该轴线可以相对于垂直取向的通道的圆柱形形状基本上遍及垂直定向的通道而结晶。晶体结构可以具有平行于垂直通道排列的第一轴线，垂直于圆柱形通道的表面对准的第二轴线等

55. 发明授权

US09349489B2 Systems and methods to update reference voltages in response to data retention in non-volatile memory 有权
标题翻译：响应于非易失性存储器中的数据保留更新参考电压的系统和方法
公开(公告)号：US09349489B2
公开(公告)日：2016-05-24
申请号：US13771894
申请日：2013-02-20
申请人： SANDISK TECHNOLOGIES INC.
发明人： Sateesh Desireddi , Jayaprakash Naradasi , Anand Venkitachalam , Manuel Antonio D'Abreu , Stephen Skala
IPC分类号： G11C29/00 , G11C29/50 , G06F12/02 , G11C11/56 , G11C16/26 , G11C16/34
CPC分类号： G11C29/50004 , G06F12/0246 , G11C11/5642 , G11C16/26 , G11C16/3495
摘要： A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count.
摘要翻译：数据存储装置包括非易失性存储器和控制器。控制器被配置为在第一时间确定具有对应于第一参考电压的电压范围内的阈值电压的存储元件的第一计数。控制器还被配置为在第二时间确定在电压范围内具有阈值电压的存储元件的第二计数。控制器还被配置为至少部分地基于第一参考电压，第一计数和第二计数来计算更新的第一参考电压。

56. 发明授权

US09349452B2 Hybrid non-volatile memory cells for shared bit line 有权
标题翻译：用于共享位线的混合非易失性存储单元
公开(公告)号：US09349452B2
公开(公告)日：2016-05-24
申请号：US13788183
申请日：2013-03-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： Mohan V. Dunga , Masaaki Higashitani
IPC分类号： G11C16/04 , H01L29/66 , H01L29/788 , G11C7/18 , G11C16/24 , H01L27/115
CPC分类号： G11C16/0425 , G11C7/18 , G11C16/0483 , G11C16/24 , H01L27/11524 , H01L27/1157 , H01L29/66825 , H01L29/788
摘要： A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements.
摘要翻译：非易失性存储系统包括多组连接的非易失性存储元件。每个组包括数据非易失性存储元件的公共侧上的多个连接的数据非易失性存储元件和多个选择栅极。多个选择栅极包括第一选择栅极和第二选择栅极。第一选择栅极具有用于组的第一子集的第一阈值电压和由于第二子集的有源区域注入导致第二阈值电压低于第二阈值电压的第二子集的第二阈值电压。第一阈值电压。每组的第二选择栅极具有可编程阈值电压。多个位线中的每一个连接到多组连接的非易失性存储元件。

57. 发明授权

US09343165B2 Dynamic drive strength optimization 有权
标题翻译：动态驱动强度优化
公开(公告)号：US09343165B2
公开(公告)日：2016-05-17
申请号：US13778894
申请日：2013-02-27
申请人： Dmitry Vaysman , Arkady Katz
发明人： Dmitry Vaysman , Arkady Katz
IPC分类号： G11C16/30 , G06F13/40
CPC分类号： G11C16/30 , G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： A system for optimizing drive strength may be utilized for identifying the maximum data transfer rate for different devices and different device configurations. The drive strength may be optimized for input/output (I/O) devices by measuring voltage drops on I/O power supply using different test patterns. The maximum drive strength is identified that satisfies a limit or threshold for the allowed voltage drop level. The test pattern may include a simultaneous toggling of each I/O device. A slew rate for the device may be utilized along with the drive strength for identifying the maximum data transfer rate.
摘要翻译：用于优化驱动强度的系统可用于识别不同设备和不同设备配置的最大数据传输速率。可以通过使用不同的测试模式测量I / O电源上的电压降，为输入/输出（I / O）器件优化驱动强度。识别满足允许的电压降电平的极限或阈值的最大驱动强度。测试模式可以包括同时切换每个I / O设备。可以利用该装置的转换速率以及用于识别最大数据传送速率的驱动强度。

58. 发明授权

US09343160B1 Erase verify in non-volatile memory 有权
标题翻译：在非易失性存储器中擦除验证
公开(公告)号：US09343160B1
公开(公告)日：2016-05-17
申请号：US14619857
申请日：2015-02-11
申请人： SanDisk Technologies Inc.
发明人： Deepanshu Dutta , Shih-Chung Lee
IPC分类号： G11C11/34 , G11C16/14 , G11C16/04 , G11C16/34 , G11C16/26
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C16/345
摘要： Reducing peak current and/or power consumption during erase verify of a non-volatile memory is disclosed. During an erase verify, memory cells are verified at a strict reference level that is deeper (e.g., lower threshold voltage) than a target reference level. After the strict erase verify, strings of memory cells that pass the strict erase verify are locked out from a next erase verify at the target reference level. Locked out strings do not conduct a significant current during erase verify, thus reducing peak current and/or power consumption.
摘要翻译：公开了在非易失性存储器的擦除验证期间降低峰值电流和/或功率消耗。在擦除验证期间，在比目标参考电平更深（例如，较低阈值电压）的严格参考电平处验证存储器单元。在严格擦除验证之后，通过严格擦除验证的存储单元串被锁定在目标参考电平的下一次擦除验证。锁定字符串在擦除验证期间不会导致显着的电流，从而降低峰值电流和/或功耗。

59. 发明授权

US09343159B2 Avoiding unintentional program or erase of a select gate transistor 有权
标题翻译：避免无意的编程或擦除选择栅晶体管
公开(公告)号：US09343159B2
公开(公告)日：2016-05-17
申请号：US14465244
申请日：2014-08-21
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Liang Pang
IPC分类号： G11C16/16 , G11C16/14 , G11C16/04 , G11C11/56 , G11C16/34
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/3418 , G11C16/3445
摘要： Techniques are provided for preventing inadvertent program or erase of select gate transistors and dummy memory cells during an erase operation involving data-storing memory cells in a three-dimensional memory device. The erase operation charges up a channel of a NAND string using gate-induced drain leakage from the select gate transistors. An erase voltage waveform and a select gate waveform are ramped up to intermediate levels which allow some charging of the channel to occur. The intermediate level of the select gate waveform is low enough to avoid inadvertent programming of the select gate transistors. Subsequently, the erase voltage waveform and the select gate waveform are ramped up to peak levels which allow additional charging of the channel to occur. The peak levels are set to avoid inadvertent erasing of the select gate transistors.
摘要翻译：提供技术用于在涉及在三维存储器件中存储存储单元的数据存储单元的擦除操作期间防止选择栅极晶体管和虚设存储单元的意外编程或擦除。擦除操作使用来自选择栅极晶体管的栅极引起的漏极泄漏来对NAND串的通道充电。擦除电压波形和选择栅极波形斜坡上升到允许通道发生一些充电的中间电平。选择栅极波形的中间电平足够低以避免选择栅极晶体管的无意编程。随后，擦除电压波形和选择栅极波形斜坡上升到峰值电平，这允许发生信道的附加充电。设置峰值电平以避免选择栅极晶体管的无意擦除。

60. 发明授权

US09343156B1 Balancing programming speeds of memory cells in a 3D stacked memory 有权
标题翻译：平衡3D堆叠存储器中存储单元的编程速度
公开(公告)号：US09343156B1
公开(公告)日：2016-05-17
申请号：US14750250
申请日：2015-06-25
申请人： SanDisk Technologies Inc.
发明人： Man L Mui , Yongke Sun , Yingda Dong
IPC分类号： G11C11/34 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2211/5621
摘要： Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells.
摘要翻译：用于三维堆叠存储器件的编程技术基于相对于字线层的边缘的组的位置来为不同组的存储器单元的不同固有编程速度提供补偿。距离边缘更大的距离与更快的编程速度相关联。在一种方法中，通过提高用于更快编程存储器单元的位线电压来使编程速度相等。也可以基于组位置来设置通过升高位线电压而触发缓慢编程模式的偏移验证电压。可以在针对一行或另一组单元的编程期间测量编程速度，以设置位线电压和/或偏移验证电压。更快编程存储单元的补偿也可以基于它们相对于较慢编程存储器单元的速度。

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