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1. 发明授权

US09710325B2 On chip dynamic read level scan and error detection for nonvolatile storage 有权
公开(公告)号：US09710325B2
公开(公告)日：2017-07-18
申请号：US14681800
申请日：2015-04-08
申请人： SanDisk Technologies Inc.
发明人： Wenzhou Chen , Zhenming Zhou , Jun Wan , Deepanshu Dutta , Yi-Chieh Chen , Dana Lee
IPC分类号： G11C16/06 , G06F11/10 , G11C16/10 , G11C11/56 , G11C16/26 , G11C16/34 , G11C29/02 , G11C16/04 , G11C29/52
CPC分类号： G06F11/1068 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/349 , G11C29/028 , G11C29/52
摘要： Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

2. 发明申请

US20170125117A1 Smart Skip Verify Mode For Programming A Memory Device 有权
公开(公告)号：US20170125117A1
公开(公告)日：2017-05-04
申请号：US14928853
申请日：2015-10-30
申请人： SANDISK TECHNOLOGIES INC.
发明人： Huai-Yuan Tseng , Deepanshu Dutta , Tai-Yuan Tseng , Grishma Shah , Muhammad Masuduzzaman
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/0409 , G11C2029/1202
摘要： Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.

3. 发明授权

US09548130B2 Non-volatile memory with prior state sensing 有权
标题翻译：具有先前状态感测的非易失性存储器
公开(公告)号：US09548130B2
公开(公告)日：2017-01-17
申请号：US14817741
申请日：2015-08-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Huai-Yuan Tseng , Dana Lee , Ken Oowada , Shih-Chung Lee
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56 , G11C16/10 , G11C16/28
CPC分类号： G11C16/3459 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/28 , H01L27/11582
摘要： A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.
摘要翻译：非易失性存储器系统包括以三维结构排列的多个存储器单元和与存储器单元通信的一个或多个控制电路。一个或多个控制电路被配置为对存储器单元编程和验证编程。多个存储器单元的验证编程包括使用第二数据状态的验证操作验证对于第一数据状态的编程。在一个实施例中，一个或多个控制电路还被配置为通过将不同的位线电压施加到不同的存储器单元来感测多个存储器单元中的不同存储单元是否处于不同的数据状态。

4. 发明申请

US20160314843A1 Non-Volatile Memory With Two Phased Programming 有权
标题翻译：具有两个相位编程的非易失性存储器
公开(公告)号：US20160314843A1
公开(公告)日：2016-10-27
申请号：US14841182
申请日：2015-08-31
申请人： SanDisk Technologies Inc.
发明人： Huai-Yuan Tseng , Deepanshu Dutta
IPC分类号： G11C16/10 , G11C16/26 , G11C16/32 , G11C11/56 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C16/3468 , G11C2211/5621
摘要： Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase. For a memory cell in the fine phase that has been verified to have reached the fine phase verify level, the memory cell will be inhibited from further programming
摘要翻译：编程非易失性存储器包括将一系列编程脉冲作为粗/精编程过程的一部分应用于存储器单元。在编程脉冲之间，针对目标数据状态的粗略相位验证电平验证粗略相位中的存储器单元，并针对目标数据状态验证精细相位中的存储单元是否存在用于目标数据状态的精细相位验证电平，响应于单个参考电压施加在公共字线上。对于已经被验证已经达到粗略相位验证电平的粗略相位的存储单元，存储器单元将暂时禁止编程用于下一个编程脉冲并切换到精细相位。对于已经验证已达到精细相位验证电平的精细相位的存储单元，存储器单元将被禁止进一步编程

5. 发明授权

US09443597B2 Controlling dummy word line bias during erase in non-volatile memory 有权
标题翻译：在非易失性存储器中擦除期间控制虚拟字线偏置
公开(公告)号：US09443597B2
公开(公告)日：2016-09-13
申请号：US14669267
申请日：2015-03-26
申请人： SanDisk Technologies Inc.
发明人： Deepanshu Dutta , Mohan Dunga , Masaaki Higashitani
IPC分类号： G11C16/16 , G11C16/14 , G11C7/10 , G11C11/56 , G11C16/04
CPC分类号： G11C16/14 , G11C7/1006 , G11C11/5635 , G11C16/0483 , G11C16/16
摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping between the select gates and the dummy storage elements.
摘要翻译：一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。选择栅极晶体管的电压也可以电容耦合得更高。衬底电压可以逐步增加和/或作为连续斜坡增加。在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。在另一种方法中，外部和内部虚拟存储元件都浮起来。由于选择栅极和虚拟存储元件之间的电荷捕获减少，存储元件的写擦除耐久性增加。

6. 发明授权

US09418751B1 Pre-program detection of threshold voltages of select gate transistors in a memory device 有权
标题翻译：对存储器件中的选择栅极晶体管的阈值电压进行预编程检测
公开(公告)号：US09418751B1
公开(公告)日：2016-08-16
申请号：US14808329
申请日：2015-07-24
申请人： SanDisk Technologies Inc.
发明人： Deepanshu Dutta , Shota Murai , Hideto Tomiie , Masaaki Higashitani
IPC分类号： G11C16/34 , G11C16/10 , G11C16/26 , G11C16/04 , G11C11/34
CPC分类号： G11C16/34 , G11C11/34 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/349 , G11C29/028
摘要： A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate transistors is evaluated, such as in response to a program, erase or read command involving a block or sub-block of memory cells. For example, a lower tail and an upper tail of the Vth distribution can be evaluated using read voltages. If the Vth is out-of-range, such as due to read disturb, data retention loss or defects in the memory device, the block or sub-block is marked as being bad and previously-programmed data in the block or sub-block can be copied to another location. If the Vth is in range, the command can be executed. Also, a control gate voltage for the select gate transistors can be set based on a Vth metric which is obtained from the evaluation.
摘要翻译：存储器件包括布置在选择栅晶体管之间的NAND串中的存储器单元。评估选择栅极晶体管的阈值电压（Vth）分布，例如响应于涉及存储器单元的块或子块的程序，擦除或读取命令。例如，可以使用读取电压来评估Vth分布的下尾和上尾。如果Vth超出范围，例如由于读取干扰，数据保留丢失或存储器件中的缺陷，则块或子块被标记为块或子块中的先前编程的数据可以复制到另一个位置。如果Vth在范围内，则可以执行命令。此外，可以基于从评估获得的Vth度量来设置用于选择栅极晶体管的控制栅极电压。

7. 发明申请

US20160118136A1 ERROR DETECTION METHOD 有权
标题翻译：错误检测方法
公开(公告)号：US20160118136A1
公开(公告)日：2016-04-28
申请号：US14525813
申请日：2014-10-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： Huai-Yuan Tseng , Deepanshu Dutta
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3495 , G11C11/5628 , G11C11/5635 , G11C13/0004 , G11C13/0035 , G11C13/0064 , G11C13/0069 , G11C16/0483 , G11C16/3422 , G11C16/349 , G11C29/52 , G11C2211/5621 , G11C2211/5644
摘要： Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming operation or an erase operation. In some cases, a Control Gate Short to Substrate (CGSS) defect, in which a control gate of a NAND memory has been shorted to the substrate, may have a defect signature in which a word line shows a deviation in the number of programming loop counts associated with programming data into memory cells connected to the word line. The deviation in the number of programming loop counts may be detected by comparing a baseline programming loop count (e.g., derived from programming a set of one or more word lines prior to programming the word line with the CGSS defect) with a programming loop count associated with programming the word line with the CGSS defect.
摘要翻译：描述了在存储器操作期间检测和校正存储器阵列中的缺陷的方法。存储器操作可以包括编程操作或擦除操作。在某些情况下，NAND存储器的控制栅极已经短路到衬底的控制栅极到基板（CGSS）缺陷可能具有缺陷签名，其中字线表示编程环路数量的偏差与将数据编程连接到与字线连接的存储器单元中的计数。可以通过比较基准编程循环计数（例如，从在编程字线与CGSS缺陷编程之前编程一组或多个字线的集合）与相关联的编程循环计数相比较来检测编程循环计数数量的偏差用CGSS缺陷对字线进行编程。

8. 发明申请

US20150200014A1 Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory 有权
标题翻译：在非易失性存储器中擦除期间控制虚拟字线偏置
公开(公告)号：US20150200014A1
公开(公告)日：2015-07-16
申请号：US14669267
申请日：2015-03-26
申请人： SanDisk Technologies Inc.
发明人： Deepanshu Dutta , Mohan Dunga , Masaaki Higashitani
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14 , G11C7/1006 , G11C11/5635 , G11C16/0483 , G11C16/16
摘要： A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping between the select gates and the dummy storage elements.
摘要翻译：一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。选择栅极晶体管的电压也可以电容耦合得更高。衬底电压可以逐步增加和/或作为连续斜坡增加。在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。在另一种方法中，外部和内部虚拟存储元件都浮起来。由于选择栅极和虚拟存储元件之间的电荷捕获减少，存储元件的写擦除耐久性增加。

9. 发明申请

US20150149693A1 Targeted Copy of Data Relocation 有权
标题翻译：数据重定位目标副本
公开(公告)号：US20150149693A1
公开(公告)日：2015-05-28
申请号：US14089061
申请日：2013-11-25
申请人： SanDisk Technologies Inc.
发明人： Yew Yin Ng , Mrinal Kochar , Niles Yang , Deepanshu Dutta
IPC分类号： G06F3/06 , G11C16/34 , G11C11/56
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0652 , G06F3/0679 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3431 , G11C16/3495 , G11C2211/5641
摘要： In a nonvolatile memory array that has a binary cache formed of SLC blocks and a main memory formed of MLC blocks, corrupted data along an MLC word line is corrected and relocated, along with any other data along the MLC word line, to binary cache, before it becomes uncorrectable. Subsequent reads of the relocated data directed to binary cache.
摘要翻译：在具有由SLC块形成的二进制高速缓存和由MLC块形成的主存储器的非易失性存储器阵列中，沿着MLC字线的损坏的数据与沿着MLC字线的任何其他数据一起被校正和重新定位到二进制高速缓存，在它变得不可纠正之前。后续读取指向二进制缓存的重定位数据。

10. 发明申请

US20150092496A1 Dynamic Bit Line Bias For Programming Non-Volatile Memory 有权
标题翻译：用于编程非易失性存储器的动态位线偏置
公开(公告)号：US20150092496A1
公开(公告)日：2015-04-02
申请号：US14561841
申请日：2014-12-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Ken Oowada , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C7/12 , G11C11/5628 , G11C16/12 , G11C16/24 , G11C16/3459
摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.
摘要翻译：用于一组非易失性存储元件的程序操作。维持以慢编程模式施加到单个存储元件的多个编程脉冲的计数，并且基于计数调整相关联的位线电压。可以使用不同的位线电压，具有公共的步长或不同的步长。结果，缓慢编程模式下的存储元件的阈值电压的变化可以使每个编程脉冲均匀，从而提高编程精度。在缓慢编程模式下，锁存器保持相关存储元件所经历的程序脉冲计数。当其阈值电压低于较低验证电平时，存储元件处于快速编程模式，而当其阈值电压处于较低验证电平和较高验证电平之间时，存储元件处于慢速编程模式。

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