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51. 发明申请

US20140177370A1 METHOD, APPARATUS AND SYSTEM FOR RESPONDING TO A ROW HAMMER EVENT 有权
标题翻译：方法，设备和系统，用于响应一个ROW HAMMER事件
公开(公告)号：US20140177370A1
公开(公告)日：2014-06-26
申请号：US13725800
申请日：2012-12-21
申请人： INTEL CORPORATION
发明人： John B. Halbert , Kuljit S. Bains
IPC分类号： G11C11/402
CPC分类号： G11C11/40618 , G06F3/0616 , G06F3/0659 , G06F3/0673 , G06F12/0646 , G06F12/0684 , G11C7/1072 , G11C11/40603 , G11C11/40611 , G11C11/4076
摘要： Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.
摘要翻译：促进存储器设备的操作模式以准备存储器中的行的目标刷新的技术和机制。在一个实施例中，存储器装置在处于来自存储器控制器的未来命令的模式中执行一个或多个操作，该命令至少部分地实现存储器的第一存储体中的行的目标刷新设备。在这样的命令之前，存储器设备从存储器控制器服务另一命令。在另一个实施例中，服务另一个命令包括存储设备访问存储器设备的第二组，同时存储设备在模式下操作，并且在预期的未来目标行刷新完成之前。

52. 发明申请

US20140177360A1 DEVICE AND METHOD FOR CONTROLLING SELF-REFRESH 有权
标题翻译：用于控制自刷新的装置和方法
公开(公告)号：US20140177360A1
公开(公告)日：2014-06-26
申请号：US13846845
申请日：2013-03-18
申请人： SK HYNIX INC.
发明人： Nam Kyu JANG , Young Geun CHOI
IPC分类号： G11C11/402
CPC分类号： G11C11/40615 , G11C5/146 , G11C11/406 , G11C11/4074
摘要： A device and method for controlling self-refresh is disclosed, which reduces current when a semiconductor device stays in a self-refresh operation. The device for controlling self-refresh includes: a bulk voltage controller configured to combine an idle signal indicating an active termination state of a bank and a self-refresh signal so as to generate a control signal for controlling a bulk voltage, a bulk voltage driver configured to vary a level of the bulk voltage in response to the control signal, and output the bulk voltage with a different level, and a refresh controller configured to output the self-refresh active signal upon receiving the bulk voltage as a bulk bias voltage.
摘要翻译：公开了一种用于控制自刷新的装置和方法，当半导体器件保持在自刷新操作中时，该装置和方法减少了电流。用于控制自刷新的装置包括：体电压控制器，被配置为组合指示存储体的活动终止状态的空闲信号和自刷新信号，以便产生用于控制体电压的控制信号;体电压驱动器被配置为响应于所述控制信号改变所述体电压的电平，并且输出具有不同电平的体电压;以及刷新控制器，被配置为在接收到所述体电压作为体偏置电压时输出所述自刷新有效信号。

53. 发明申请

US20130315019A1 REFRESH CIRCUITS 有权
标题翻译：刷新电路
公开(公告)号：US20130315019A1
公开(公告)日：2013-11-28
申请号：US13716041
申请日：2012-12-14
申请人： SK HYNIX INC.
发明人： Dong Kyun Kim
IPC分类号： G11C11/402 , H03L7/00
CPC分类号： G11C11/402 , G11C11/40615 , G11C11/40626 , H03B19/14 , H03L1/022 , H03L1/027 , H03L7/00
摘要： A refresh circuit includes a period signal generation circuit configured to drive a control node according to a level of the control node, discharge first and second currents from the control node in response to the first temperature signal, and generate a period signal, a division signal generator configured to divide the period signal to generate a first division signal and a second division signal, and a selector configured to select one of the first and second division signals in response to a second temperature signal and for outputting the selected division signal as a refresh signal.
摘要翻译：刷新电路包括周期信号生成电路，被配置为根据控制节点的电平驱动控制节点，响应于第一温度信号从控制节点放电第一和第二电流，并产生周期信号，分频信号发生器，其被配置为分频所述周期信号以产生第一除法信号和第二除法信号;以及选择器，被配置为响应于第二温度信号选择所述第一和第二除法信号中的一个，并将所选择的除法信号作为刷新输出信号。

54. 发明申请

US20130272082A1 REFRESH CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件中的刷新电路
公开(公告)号：US20130272082A1
公开(公告)日：2013-10-17
申请号：US13770538
申请日：2013-02-19
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Young-Hun Kim , Inchul Jeong
IPC分类号： G11C11/402 , G11C7/12
CPC分类号： G11C11/402 , G11C7/12 , G11C11/40615 , G11C11/40618
摘要： A refresh circuit in a semiconductor memory device performs a multi-enable skew refresh operation during each periodic refresh operation. The refresh circuit includes a signal generation unit configured to generate a plurality of refresh signals having different timings during a refresh operation period, a first refresh circuit configured to enable refresh target lines associated with a first memory group in a memory cell array through operation periods of at least two time periods by using some of the refresh signals, and a second refresh circuit configured to enable refresh target lines associated with a second memory group differing from the first memory group through operation periods of at least two time periods by using some or all of the rest of the refresh signals. Enable timings of the first and second refresh circuits do not coincide each other.
摘要翻译：半导体存储器件中的刷新电路在每个周期性刷新操作期间执行多使能偏斜刷新操作。刷新电路包括：信号生成单元，被配置为在刷新操作期间生成具有不同定时的多个刷新信号;第一刷新电路，被配置为使存储单元阵列中与第一存储器组相关联的刷新目标线通过操作周期通过使用一些刷新信号的至少两个时间段，以及第二刷新电路，被配置为通过使用一些或全部的操作来使能与第一存储器组不同的第二存储器组的刷新目标线通过至少两个时间段的操作周期剩下的刷新信号。启用第一和第二刷新电路的定时不一致。

55. 发明申请

US20130155782A1 RANDOM ACCESS MEMORY AND REFRESH CONTROLLER THEREOF 有权
标题翻译：随机存取存储器和刷新控制器
公开(公告)号：US20130155782A1
公开(公告)日：2013-06-20
申请号：US13329337
申请日：2011-12-19
申请人： Ying-Te Tu
发明人： Ying-Te Tu
IPC分类号： G11C11/402 , G11C7/10
CPC分类号： G11C11/406 , G11C11/4085 , G11C2211/4065
摘要： A random access memory and a refresh controller thereof are provided. The refresh controller includes a write action detector, a latch device, a reset circuit, and a refresh masking device. The write action detector is coupled to an address decoder of the random access memory, and is used to detect a write action in an address corresponding to the address decoder and generate a detection result. The latch device is coupled to the write action detector, and is used to receive and latch the detection result. The reset circuit is coupled to the latch device, receives a reset control signal, and resets the detection result according to the reset control signal. The refresh masking device is coupled to a corresponding word line control circuit and the latch device and is used to mask a refresh action on the word line control circuit according to the detection result.
摘要翻译：提供随机存取存储器及其刷新控制器。刷新控制器包括写入动作检测器，锁存器件，复位电路和刷新屏蔽器件。写入动作检测器耦合到随机存取存储器的地址解码器，并且用于检测与地址解码器相对应的地址中的写入动作并产生检测结果。锁存装置耦合到写入动作检测器，并用于接收和锁存检测结果。复位电路耦合到锁存器件，接收复位控制信号，并根据复位控制信号复位检测结果。刷新掩蔽装置被耦合到相应的字线控制电路和锁存装置，并用于根据检测结果屏蔽字线控制电路上的刷新动作。

56. 发明申请

US20130114364A1 SEMICONDUCTOR DEVICE PERFORMING REFRESH OPERATION 有权
公开(公告)号：US20130114364A1
公开(公告)日：2013-05-09
申请号：US13670802
申请日：2012-11-07
申请人： Elpida Memory, Inc.
发明人： Kenichi SAKAKIBARA , Toru Ishikawa
IPC分类号： G11C11/402
CPC分类号： G11C11/40626 , G11C11/40618 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a device that includes a first semiconductor chip. The first semiconductor chip includes a first data storage area storing data, a first refresh circuit repeating a first refresh operation on the first data storage area to make the first data storage area retain the data, a first terminal supplied with a first control signal from outside of the first semiconductor chip, and a first control circuit coupled between the first terminal and the first refresh circuit to control a repetition cycle of the first refresh operation in response to the first control signal.

57. 发明申请

US20130094317A1 REFRESH CONTROL CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS 审中-公开
标题翻译：冷却控制电路和半导体器件的方法
公开(公告)号：US20130094317A1
公开(公告)日：2013-04-18
申请号：US13602066
申请日：2012-08-31
申请人： Jeong Woo LEE
发明人： Jeong Woo LEE
IPC分类号： G11C11/402
CPC分类号： G11C11/40618
摘要： A refresh control circuit of a semiconductor apparatus includes: a first bank refresh counter configured to increase or decrease a logic value of a first refresh address signal when a first bank address signal is enabled during a refresh operation, a second bank refresh counter configured to increase or decrease a logic value of a second refresh address signal when a second bank address signal is enabled during the refresh operation, a bank selection unit configured to generate first and second bank select signals in response to the first and second bank address signals during the refresh operation, and a row selection unit configured to generate first and second row select signals in response to the first and second refresh address signals and the first and second bank select signals.
摘要翻译：半导体装置的刷新控制电路包括：第一存储体刷新计数器，被配置为当刷新操作期间启用第一存储体地址信号时增加或减少第一刷新地址信号的逻辑值，第二存储体刷新计数器被配置为增加或者在刷新操作期间启用第二存储体地址信号时减小第二刷新地址信号的逻辑值;存储体选择单元，被配置为在刷新期间响应于第一和第二存储区地址信号产生第一和第二存储体选择信号操作和行选择单元，被配置为响应于第一和第二刷新地址信号以及第一和第二存储体选择信号而产生第一和第二行选择信号。

58. 发明申请

US20130088931A1 ASYMMETRIC MEMORY CELLS 有权
标题翻译：不对称记忆细胞
公开(公告)号：US20130088931A1
公开(公告)日：2013-04-11
申请号：US13269942
申请日：2011-10-10
申请人： George M. BRACERAS , Krishnan S. RENGARAJAN
发明人： George M. BRACERAS , Krishnan S. RENGARAJAN
IPC分类号： G11C7/12 , G11C11/402
CPC分类号： G11C7/20 , G11C11/412
摘要： An asymmetric memory cell is disclosed. The memory cell includes a refresh control line, a pass gate transistor, and a refresh transistor. The refresh transistor is coupled to the refresh control line, and provides a feedback between the pass gate transistor and a plurality of inverters, when the refresh control line is in a default state.
摘要翻译：公开了一种非对称存储器单元。存储单元包括刷新控制线，通栅晶体管和刷新晶体管。当刷新控制线处于默认状态时，刷新晶体管耦合到刷新控制线，并且在通过栅极晶体管和多个反相器之间提供反馈。

59. 发明申请

US20130003451A1 REFRESH ARCHITECTURE AND ALGORITHM FOR NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的刷新架构和算法
公开(公告)号：US20130003451A1
公开(公告)日：2013-01-03
申请号：US13513139
申请日：2009-12-02
申请人： Ferdinando Bedeschi , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Roberto Gastaldi
IPC分类号： G11C11/402 , G11C11/00
CPC分类号： G11C13/0033 , G06F11/1068 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C14/009 , G11C16/3418 , G11C29/52
摘要： Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
摘要翻译：刷新非易失性存储器件的方法和系统，例如相变存储器。在一个实施例中，作为系统状态的函数，存储器设备使用边缘读取参考电平或使用非余量读取参考电平对错误校正的存储器单元的第二刷新来执行存储器单元的第一刷新。

60. 发明申请

US20120106283A1 Row Address Control Circuit Semiconductor Memory Device Including The Same And Method Of Controlling Row Address 失效
标题翻译：行地址控制电路包括相同的半导体存储器件和控制行地址的方法
公开(公告)号：US20120106283A1
公开(公告)日：2012-05-03
申请号：US13237353
申请日：2011-09-20
申请人： Hui-Kap Yang , Woo-Seop Jeong , Chul-Sung Park
发明人： Hui-Kap Yang , Woo-Seop Jeong , Chul-Sung Park
IPC分类号： G11C11/402 , G11C8/00 , G11C8/04
CPC分类号： G11C29/20 , G11C2029/1802
摘要： A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.
摘要翻译：包括动态存储单元的半导体存储器件的行地址控制电路包括测试模式设置单元，地址计数器和行地址生成单元。测试模式设置单元被配置为响应于测试命令提供指示是否执行测试操作的测试模式信号; 地址计数器被配置为生成逐渐增加的第一地址; 并且行地址生成单元被配置为基于测试模式信号选择性地选择第一地址和第二地址中的一个作为刷新地址，第二地址被外部提供。

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