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51. 发明授权

US08445991B2 Semiconductor device with MIM capacitor and method for manufacturing the same 有权
标题翻译：具有MIM电容器的半导体器件及其制造方法
公开(公告)号：US08445991B2
公开(公告)日：2013-05-21
申请号：US12985812
申请日：2011-01-06
申请人： Jin-Youn Cho , Young-soo Kang , Sang-Geun Koo
发明人： Jin-Youn Cho , Young-soo Kang , Sang-Geun Koo
IPC分类号： H01L29/92
CPC分类号： H01L28/60 , H01L21/31144 , H01L28/65 , H01L28/75
摘要： A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件包括形成在基板上的下电极，包括蚀刻介电区域和形成在下电极上的生长电介质区域的电介质层，形成在生长电介质区域上的上电极，形成在其上的硬掩模上电极，形成在硬掩模的侧表面和上电极以及蚀刻的电介质区域的表面上的隔离物，以及形成在硬掩模和间隔物上的缓冲绝缘层。

52. 发明申请

US20130119512A1 Top Electrode Templating for DRAM Capacitor 有权
标题翻译：用于DRAM电容器的顶部电极模板
公开(公告)号：US20130119512A1
公开(公告)日：2013-05-16
申请号：US13665524
申请日：2012-10-31
申请人： Intermolecular, Inc. , Elpida Memory, Inc
发明人： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Hiroyuki Ode
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01L21/02186 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/02356 , H01L27/10852 , H01L28/75
摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
摘要翻译：用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。高k电介质层包括可在随后的退火处理后结晶的掺杂材料。金属氧化物第二电极层形成在电介质层的上方。金属氧化物第二电极层具有与电介质层的晶体结构相容的晶体结构。可选地，在金属氧化物第二电极层上形成第二电极体层。

53. 发明申请

US20130099355A1 MEMS Structures and Methods for Forming the Same 有权
公开(公告)号：US20130099355A1
公开(公告)日：2013-04-25
申请号：US13280075
申请日：2011-10-24
申请人： Ping-Yin Liu , Xin-Hua Huang , Hsin-Ting Huang , Yuan-Chih Hsieh , Jung-Huei Peng , Lan-Lin Chao , Chia-Shiung Tsai , Chun-Wen Cheng
发明人： Ping-Yin Liu , Xin-Hua Huang , Hsin-Ting Huang , Yuan-Chih Hsieh , Jung-Huei Peng , Lan-Lin Chao , Chia-Shiung Tsai , Chun-Wen Cheng
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： B81B7/0058 , B81B3/0005 , B81B3/0021 , B81C1/00269 , B81C1/00793 , B81C2201/053 , B81C2203/0109 , H01G5/16 , H01L28/60
摘要： A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer

54. 发明申请

US20130099354A1 CAPACITOR WITH DEEP TRENCH ION IMPLANTATION 失效
标题翻译：电容器与深层离子植入
公开(公告)号：US20130099354A1
公开(公告)日：2013-04-25
申请号：US13279877
申请日：2011-10-24
申请人： Chengwen Pei , Roger Allen Booth, JR. , Herbert Lei Ho , Naoyoshi Kusaba
发明人： Chengwen Pei , Roger Allen Booth, JR. , Herbert Lei Ho , Naoyoshi Kusaba
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L29/945 , H01L29/66181
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.
摘要翻译：公开了一种改进的半导体电容器和制造方法。实施例利用深沟槽，然后通过在沟槽内部执行预非晶体植入来将沟槽的内表面转变为非晶硅来处理，以消除可能降低电容器性能的耗尽区。

55. 发明申请

US20130082351A1 Method for Fabricating a MIM Capacitor Having a Local Interconnect Metal Electrode and Related Structure 有权
标题翻译：具有局部互连金属电极和相关结构的MIM电容器的制造方法
公开(公告)号：US20130082351A1
公开(公告)日：2013-04-04
申请号：US13248823
申请日：2011-09-29
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
摘要翻译：根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器形成在底部电容器电极上的层间势垒电介质上的电极。顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。在一个实施例中，底部电容器电极由栅极金属形成。该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

56. 发明申请

US20130069200A1 METHOD OF FORMING A ROBUST, MODULAR MIM CAPACITOR WITH IMPROVED CAPACITANCE DENSITY 有权
标题翻译：形成具有改善电容密度的稳定的模块化MIM电容器的方法
公开(公告)号：US20130069200A1
公开(公告)日：2013-03-21
申请号：US13239192
申请日：2011-09-21
申请人： Venkat Raghavan , Andrew Strachan
发明人： Venkat Raghavan , Andrew Strachan
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90
摘要： A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilsicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack an don exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.
摘要翻译：形成电容器结构的方法包括：在下面的介电层上形成掺杂的多晶硅层; 在所述掺杂多晶硅层上形成电介质叠层; 在所述电介质堆叠中形成接触孔以暴露所述掺杂聚硅氧烷层的表面区域; 形成填充所述接触孔并与所述掺杂多晶硅层的暴露表面接触的导电接触插塞; 在所述电介质堆叠中形成多个沟槽，使得每个沟槽暴露所述掺杂多晶硅层的对应表面区域; 在所述电介质堆叠的暴露表面上形成导电底部电容器板，以及所述掺杂多晶硅层的暴露表面; 在底部电容器板上形成电容器电介质层; 以及在所述电容器介电层上形成导电顶部电容器板。

57. 发明授权

US08395235B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08395235B2
公开(公告)日：2013-03-12
申请号：US12861219
申请日：2010-08-23
申请人： Keiichi Tsuchiya
发明人： Keiichi Tsuchiya
IPC分类号： H01L29/92
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852
摘要： A semiconductor device may include, but is not limited to a first electrode upwardly extending, and a second electrode upwardly extending along the first electrode. The first electrode includes a lower portion and an upper portion. The second electrode covers a bottom surface and an outer side surface of the lower portion of the first electrode. The upper portion of the first electrode is positioned higher than the second electrode.
摘要翻译：半导体器件可以包括但不限于向上延伸的第一电极和沿着第一电极向上延伸的第二电极。第一电极包括下部和上部。第二电极覆盖第一电极的下部的底面和外侧面。第一电极的上部位于第二电极的上方。

58. 发明申请

US20130056852A1 Methods For Depositing High-K Dielectrics 有权
标题翻译：沉积高K电介质的方法
公开(公告)号：US20130056852A1
公开(公告)日：2013-03-07
申请号：US13668488
申请日：2012-11-05
申请人： Intermolecular, Inc.
发明人： Imran Hashim , Edward L. Haywood , Sandra G. Malhotra , Xiangxin Rui , Sunil Shanker
IPC分类号： H01L29/92
CPC分类号： H01L21/3141 , C23C16/02 , C23C16/405 , H01L21/02186 , H01L21/02271 , H01L21/02315 , H01L21/31604 , H01L28/91
摘要： Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.
摘要翻译：描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种在暴露的金属上沉积氧化钛层，其中所述氧化钛层包含至少一部分金红石型氧化钛。

59. 发明申请

US20130043561A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130043561A1
公开(公告)日：2013-02-21
申请号：US13657325
申请日：2012-10-22
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Wensheng Wang
IPC分类号： H01L29/92
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/65 , H01L28/75
摘要： A semiconductor device includes a capacitor dielectric film formed on a lower electrode and made of a ferroelectric material, and an upper electrode formed on a capacitor dielectric film, wherein the lower electrode includes a lowest conductive layer and an upper conductive layer, the lowest conductive layer being made of a noble metal other than iridium, and the upper conductive layer being formed on the lowest conductive layer and made of a conductive material, which is different from a material for the lowest conductive layer, and which is other than platinum.
摘要翻译：半导体器件包括形成在下电极上并由铁电材料制成的电容器电介质膜和形成在电容器电介质膜上的上电极，其中下电极包括最低导电层和上导电层，最低导电层由除铱之外的贵金属制成，并且所述上导电层形成在最低导电层上，并且由不同于用于最低导电层的材料的不同于铂的导电材料制成。

60. 发明申请

US20130037859A1 SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其编程方法
公开(公告)号：US20130037859A1
公开(公告)日：2013-02-14
申请号：US13321852
申请日：2011-08-12
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/326 , H01L23/522 , H01L29/788 , H01L29/92 , H01L23/525
CPC分类号： H01L23/481 , H01L23/525 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.
摘要翻译：提供了半导体器件及其编程方法。半导体器件包括：其中形成有互连的半导体衬底; 穿透半导体衬底的透硅通孔（TSV）; 以及可以在导通和关断状态之间切换的可编程器件，TSV通过可编程器件连接到互连。本发明有利于提高TSV应用的灵活性。

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