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51. 发明授权

US08716077B2 Replacement gate compatible eDRAM transistor with recessed channel 有权
标题翻译：具有凹槽通道的替换门兼容eDRAM晶体管
公开(公告)号：US08716077B2
公开(公告)日：2014-05-06
申请号：US13215635
申请日：2011-08-23
申请人： Till Schloesser , Peter Baars , Frank Jakubowski
发明人： Till Schloesser , Peter Baars , Frank Jakubowski
IPC分类号： H01L21/336 , H01L21/8242
CPC分类号： H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/42356 , H01L29/4236 , H01L29/42364 , H01L29/42372 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66621 , H01L29/78 , H01L29/7833 , H01L29/7848
摘要： An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.
摘要翻译：一种eDRAM被制造成包括高性能逻辑晶体管技术和超低泄漏DRAM晶体管技术。实施例包括在衬底中形成凹陷通道，在衬底的上表面的一部分上形成第一栅极氧化物至衬底通道的第一厚度和形成第二厚度的第二栅极氧化物，在凹陷部分中形成第一多晶硅栅极在所述第二栅极氧化物上形成第二多晶硅栅极，在所述第一和第二多晶硅栅极中的每一个的相对侧上形成间隔物，去除形成第一和第二空腔的第一和第二多晶硅栅极， k电介质层，并且分别在第一和第二空腔中形成第一和第二金属栅极。

52. 发明授权

US08685815B2 Hafnium tantalum titanium oxide films 有权
标题翻译：铪钽氧化钛薄膜
公开(公告)号：US08685815B2
公开(公告)日：2014-04-01
申请号：US13849970
申请日：2013-03-25
申请人： Micron Technology, Inc.
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/02 , H01L21/8238 , H01L21/8242 , H01L21/336 , H01L21/469 , H01L27/108 , H01L29/94 , H01L29/788
CPC分类号： H01L21/02194 , H01L21/0228 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/3142 , H01L21/31637 , H01L21/31645 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66825
摘要： Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition.
摘要翻译：构成为一个或多个单层的包含铪钽氧化钛膜的电介质层的实施例包括设置在晶体管中的电介质层。一个实施方案可以包括使用单层或部分单层测序方法如反应序列原子层沉积来形成铪钽氧化钛膜。

53. 发明授权

US08674420B2 Semiconductor devices including buried gate electrodes and methods of forming semiconductor devices including buried gate electrodes 有权
标题翻译：包括掩埋栅电极的半导体器件和形成包括掩埋栅电极的半导体器件的方法
公开(公告)号：US08674420B2
公开(公告)日：2014-03-18
申请号：US12588111
申请日：2009-10-05
申请人： Kye-Hee Yeom
发明人： Kye-Hee Yeom
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/105 , H01L27/10814 , H01L27/10885 , H01L27/10894
摘要： A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, a plurality of buried gate electrodes extending below an upper surface of the semiconductor device, and a plurality of bit lines extending along a first direction over the semiconductor substrate, wherein the plurality of bit lines are connected to corresponding ones of the active regions of the semiconductor substrate, and at least a portion of the bit lines extend along a same and/or substantially same plane as an upper surface of the corresponding active region to which it is connected.
摘要翻译：一种半导体器件，包括：半导体衬底，包括限定半导体衬底的有源区的隔离;在半导体器件的上表面下方延伸的多个掩埋栅电极;以及沿半导体衬底上的第一方向延伸的多个位线; 其中所述多个位线连接到所述半导体衬底的相应的有源区，并且所述位线的至少一部分沿着与所述对应有源区的上表面相同和/或基本相同的平面延伸，它是连接的。

54. 发明授权

US08673719B2 DRAM with a nanowire access transistor 有权
标题翻译：具有纳米线存取晶体管的DRAM
公开(公告)号：US08673719B2
公开(公告)日：2014-03-18
申请号：US13774682
申请日：2013-02-22
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Jeffrey W. Sleight
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8242
CPC分类号： H01L27/10805 , B82Y10/00 , H01L21/84 , H01L27/0207 , H01L27/10873 , H01L27/1203 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/945 , Y10S977/89 , Y10S977/943
摘要： A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
摘要翻译：半导体纳米线与环绕半导体部分整体形成，该环绕半导体部分接触位于深沟槽的上部并且与深沟槽电容器的内部电极接触的导电盖结构的侧壁。半导体纳米线从掩埋绝缘体层的上方悬挂。在包括半导体纳米线和环绕半导体部分的图案化半导体材料结构的表面上形成栅极电介质层。围绕半导体纳米线的中心部分形成环形栅电极部分，形成栅极间隔物。去除图案化的半导体材料结构的物理曝光部分，并且执行选择性外延和金属化以将半导体纳米线的源极端部连接到导电帽结构。

55. 发明授权

US08647944B2 Semiconductor device and semiconductor device manufacturing method 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US08647944B2
公开(公告)日：2014-02-11
申请号：US13927855
申请日：2013-06-26
申请人： Renesas Electronics Corporation
发明人： Hiroki Shinkawata
IPC分类号： H01L21/8242
CPC分类号： H01L29/66477 , H01L21/28518 , H01L27/1052 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.
摘要翻译：一种半导体器件，包括具有形成逻辑器件的逻辑形成区域的半导体衬底; 形成在所述逻辑形成区域中的所述半导体衬底的上表面中的第一杂质区; 形成在所述逻辑形成区域中的所述半导体衬底的上表面中的第二杂质区; 第三杂质区，形成在所述第一杂质区的上表面，并且具有不同于所述第二杂质区的导电型; 第四区域，形成在所述第二杂质区域的上表面中，并且具有不同于所述第二杂质区域的导电型; 形成在第三杂质区的上表面的第一硅化物膜; 形成在所述第四杂质区的上表面中并且具有比所述第一硅化物膜更大的厚度的第二硅化物膜。

56. 发明授权

US08642423B2 Polysilicon/metal contact resistance in deep trench 有权
公开(公告)号：US08642423B2
公开(公告)日：2014-02-04
申请号：US13307874
申请日：2011-11-30
申请人： Brian W. Messenger , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
发明人： Brian W. Messenger , Paul C. Parries , Chengwen Pei , Geng Wang , Yanli Zhang
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10829 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L27/1087 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

57. 发明授权

US08633036B2 Manufacturing method of ferroelectric capacitor 有权
标题翻译：铁电电容器的制造方法
公开(公告)号：US08633036B2
公开(公告)日：2014-01-21
申请号：US13412939
申请日：2012-03-06
申请人： Kouichi Nagai
发明人： Kouichi Nagai
IPC分类号： H01L21/00 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/11509 , H01L28/55 , H01L28/65 , H01L28/75
摘要： Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.
摘要翻译：提供了一种铁电存储器，其包括硅衬底，形成在硅衬底上的晶体管和形成在晶体管上方的铁电电容器。铁电电容器包括下电极，形成在下电极上的铁电膜，形成在强电介质膜上的上电极和形成在上电极上的金属膜。

58. 发明授权

US08627258B2 Adjusting capacitance of capacitors without affecting die area 失效
标题翻译：电容器的调整电容，不影响芯片面积
公开(公告)号：US08627258B2
公开(公告)日：2014-01-07
申请号：US13592765
申请日：2012-08-23
申请人： Peter Huang , Ming-Chun Chen
发明人： Peter Huang , Ming-Chun Chen
IPC分类号： G06F17/50 , H01L21/20 , H01L27/108 , H01L29/12 , H01L29/786 , H01L29/94 , H01L21/338 , H01L21/337 , H01L21/8242
CPC分类号： H01G4/33 , H01L22/14 , H01L22/20 , H01L27/0207 , H01L27/118 , H01L28/86
摘要： According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.
摘要翻译：根据一个示例性实施例，一种用于调整电容器几何形状的方法包括制造驻留在具有第一组工艺参数的第一标准单元中的第一复合电容器。该方法还包括使用具有与第一标准单元基本相同的尺寸的第二标准单元。该方法还包括使用来自第一复合电容器的电容值来调整驻留在第二标准单元中的第二复合电容器的几何形状，其中第二复合电容器由第二组工艺参数制成。可以调整第二复合电容器的几何形状，使得第二复合电容器的电容值基本上等于来自第一复合电容器的电容值。

59. 发明授权

US08609457B2 Semiconductor device with DRAM bit lines made from same material as gate electrodes in non-memory regions of the device, and methods of making same 有权
标题翻译：具有与器件的非存储区域中的栅电极相同材料制成的DRAM位线的半导体器件及其制造方法
公开(公告)号：US08609457B2
公开(公告)日：2013-12-17
申请号：US13099692
申请日：2011-05-03
申请人： Peter Baars , Till Schloesser , Frank Jakubowski
发明人： Peter Baars , Till Schloesser , Frank Jakubowski
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10885
摘要： Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.
摘要翻译：通常，本公开涉及一种具有由与器件的非存储区域中的栅电极相同的材料制成的DRAM位线的半导体器件及其制造方法。本文公开的一种说明性方法包括形成包括存储器阵列和逻辑区域的半导体器件。所述方法还包括在所述存储器阵列中形成掩埋字线，并且在形成所述掩埋字线之后，执行第一公共处理操作以形成所述逻辑区域中的导电栅电极的至少一部分并且形成至少一部分的存储器阵列中的导电位线。

60. 发明申请

US20130328116A1 DRAM WITH A NANOWIRE ACCESS TRANSISTOR 有权
标题翻译：具有纳米访问晶体管的DRAM
公开(公告)号：US20130328116A1
公开(公告)日：2013-12-12
申请号：US13490759
申请日：2012-06-07
申请人： Josephine B. Chang , Jeffrey W. Sleight
发明人： Josephine B. Chang , Jeffrey W. Sleight
IPC分类号： H01L27/108 , H01L21/8242 , B82Y99/00
CPC分类号： H01L27/10805 , B82Y10/00 , H01L21/84 , H01L27/0207 , H01L27/10873 , H01L27/1203 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/945 , Y10S977/89 , Y10S977/943
摘要： A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.
摘要翻译：半导体纳米线与环绕半导体部分整体形成，该环绕半导体部分接触位于深沟槽的上部并且与深沟槽电容器的内部电极接触的导电盖结构的侧壁。半导体纳米线从掩埋绝缘体层的上方悬挂。在包括半导体纳米线和环绕半导体部分的图案化半导体材料结构的表面上形成栅极电介质层。围绕半导体纳米线的中心部分形成环形栅电极部分，形成栅极间隔物。去除图案化的半导体材料结构的物理曝光部分，并且执行选择性外延和金属化以将半导体纳米线的源极端部连接到导电帽结构。

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