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1. 发明授权

US10229922B2 Methods of forming memory devices with isolation structures 有权
公开(公告)号：US10229922B2
公开(公告)日：2019-03-12
申请号：US15153036
申请日：2016-05-12
申请人： MICRON TECHNOLOGY, INC.
发明人： Badih El-Kareh , Leonard Forbes
IPC分类号： H01L21/76 , H01L27/11524 , H01L21/28 , H01L27/115 , H01L27/11521 , H01L29/66 , H01L29/788 , G11C16/04 , G11C16/10 , H01L29/06
摘要： A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.

2. 发明申请

US20160020322A1 METHODS OF FORMING STRAINED SEMICONDUCTOR CHANNELS 有权
标题翻译：形成应变半导体通道的方法
公开(公告)号：US20160020322A1
公开(公告)日：2016-01-21
申请号：US14869546
申请日：2015-09-29
申请人： Micron Technology, Inc.
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A. Farrar
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/265
CPC分类号： H01L29/7846 , H01L21/26506 , H01L21/7621 , H01L21/76232 , H01L29/0653 , H01L29/66568 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/7849
摘要： In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.
摘要翻译：在各种方法实施例中，限定半导体衬底中的器件区域和与器件区域相邻的隔离区域。器件区域具有沟道区域，并且隔离区域具有与沟道区域横向相邻的应变诱导区域。通道区域应变为用于载流子迁移率增强的期望应变，其中至少一种离子型注入能量，从而在隔离区域的应变诱导区域中产生峰值注入。本文提供了其它方面和实施例。

3. 发明授权

US09231047B2 Capacitors and methods with praseodymium oxide insulators 有权
标题翻译：电容器和方法与氧化镨绝缘子
公开(公告)号：US09231047B2
公开(公告)日：2016-01-05
申请号：US14518723
申请日：2014-10-20
申请人： Micron Technology, Inc.
发明人： Kie Y. Ahn , Leonard Forbes , Arup Bhattacharyya
IPC分类号： H01L21/02 , H01L49/02 , C23C16/30 , C23C16/40 , H01G4/08 , H01G4/12 , H01G4/33 , H01L21/316
CPC分类号： H01L28/60 , C23C16/308 , C23C16/40 , H01G4/085 , H01G4/1209 , H01G4/33 , H01L21/02192 , H01L21/022 , H01L21/02244 , H01L21/0228 , H01L21/31683 , H01L28/40 , H01L28/90
摘要： Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
摘要翻译：示出了通过这些方法形成的形成的电容器和形成的电容器。将含有镨的单层沉积在基底上，随后进行处理以形成氧化镨电介质。将含有钛或其他金属的单层沉积在基底上，随后加工形成金属电极。所得的电容器结构包括诸如改进的尺寸控制的特性。一个改进的尺寸控制包括厚度。一些所得的电容器结构还包括诸如无定形或纳米晶体微结构的性质。使用这些方法形成的电容器的选定部件具有比衬底形貌更好的阶梯覆盖和更强的膜机械性能。

4. 发明申请

US20150262643A1 VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME 审中-公开
标题翻译：垂直晶体管，存储单元，器件，系统及其形成方法
公开(公告)号：US20150262643A1
公开(公告)日：2015-09-17
申请号：US14725776
申请日：2015-05-29
申请人： Micron Technology, Inc.
发明人： Leonard Forbes
IPC分类号： G11C11/407 , G11C11/408
CPC分类号： G11C11/407 , G11C11/404 , G11C11/4085 , H01L21/8239 , H01L27/1052 , H01L27/10873 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. A first gate is coupled to a first side of the semiconductor pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.
摘要翻译：公开了一种与包括从整体连接的半导体衬底向外延伸的半导体柱的垂直存储单元相关的存储器件，系统和制造方法。第一源/漏区形成在半导体衬底中，并且在半导体柱内形成体区和第二源/漏区。第一栅极耦合到半导体柱的第一侧，用于当激活时将第一和第二源/漏区耦合在一起。垂直存储单元还包括形成在半导体柱的延伸端上并电耦合到第二源/漏区的存储电容器。

5. 发明申请

US20150171165A1 BONDED STRAINED SEMICONDUCTOR WITH A DESIRED SURFACE ORIENTATION AND CONDUCTANCE DIRECTION 审中-公开
标题翻译：具有所需表面方向和导电方向的粘结应变半导体
公开(公告)号：US20150171165A1
公开(公告)日：2015-06-18
申请号：US14628825
申请日：2015-02-23
申请人： MICRON TECHNOLOGY, INC.
发明人： Leonard Forbes
IPC分类号： H01L29/10 , H01L29/04 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/045 , H01L29/1037 , H01L29/66651 , H01L29/7843 , H01L29/7849
摘要： According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor layer. Various embodiments provide a tensile strain, and various embodiments provide a compressive strain. Other aspects and embodiments are provided herein.
摘要翻译：根据各种方法实施例，半导体层被定向到衬底。半导体层具有表面取向并且被定向到衬底以提供用于表面取向的期望的电导方向。取向半导体层与基板结合以使半导体层变形。各种实施例提供拉伸应变，并且各种实施例提供压缩应变。本文提供了其它方面和实施例。

6. 发明授权

US08907486B2 Ruthenium for a dielectric containing a lanthanide 有权
标题翻译：用于含有镧系元素的电介质的钌
公开(公告)号：US08907486B2
公开(公告)日：2014-12-09
申请号：US14052483
申请日：2013-10-11
申请人： Micron Technology, Inc.
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L21/31 , H01L29/51 , H01L21/28
CPC分类号： H01L21/28 , H01G4/085 , H01G4/20 , H01G4/33 , H01L21/28194 , H01L21/28273 , H01L29/517
摘要： A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide.
摘要翻译：包含含有镧系元素的氧化物的电介质的钌的栅极和制造这种组合栅极和电介质的方法产生用于各种电子器件的可靠结构。可以在镧系元素氧化物上形成钌或导电氧化钌栅极。在镧系元素氧化物上的基于钌的栅极提供能够有效地防止栅极和镧系元素氧化物之间的反应的栅极结构。

7. 发明申请

US20140246651A1 GROWN NANOFIN TRANSISTORS 审中-公开
标题翻译： GRAN NANOFIN晶体管
公开(公告)号：US20140246651A1
公开(公告)日：2014-09-04
申请号：US14276473
申请日：2014-05-13
申请人： Micron Technology, Inc.
发明人： Leonard Forbes
IPC分类号： H01L29/06 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/0665 , H01L21/823431 , H01L27/0886 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L29/0673 , H01L29/42392 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallise the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallised semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
摘要翻译：本主题的一个方面涉及一种用于形成晶体管的方法。根据实施例，在晶体衬底上形成非晶半导体材料的翅片，并且进行固相外延（SPE）工艺以使非晶半导体材料使用晶体衬底结晶以使结晶生长晶种。翅片具有小于最小特征尺寸的至少一个方向的横截面厚度。在第一源极/漏极区域和第二源极/漏极区域之间的晶体管半导体柱中形成晶体管本体。周围的栅极绝缘体形成在半导体柱周围，周围的栅极通过周围的栅极绝缘体形成在半导体柱周围并与半导体柱分离。本文提供了其他方面。

8. 发明申请

US20140084355A1 APPARATUS HAVING A DIELECTRIC CONTAINING SCANDIUM AND GADOLINIUM 有权
标题翻译：具有电介质含有SCANIUM和GADOLINIUM的装置
公开(公告)号：US20140084355A1
公开(公告)日：2014-03-27
申请号：US14099107
申请日：2013-12-06
申请人： Micron Technology, Inc.
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L29/51 , H01L29/788
CPC分类号： H01L21/02192 , C23C16/40 , C23C16/45529 , C23C16/4554 , C23C16/45553 , H01L21/022 , H01L21/0228 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L21/3142 , H01L21/31604 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/788 , H01L29/792
摘要： Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.
摘要翻译：具有包含钪和钆的电介质的装置可以提供具有高介电常数（高k）的可靠结构。在一个实施方案中，可以使用单层或部分单层序列方法，例如原子层沉积（ALD）来形成含氧化钆和氧化钪的电介质。在一个实施例中，可以通过使用前体化学品将原子层沉积氧化钆沉积到衬底表面上，然后使用前体化学品将氧化钪沉积到衬底上并重复形成薄的层压结构来形成电介质结构。含有钪和钆的电介质可用作MOSFET的栅极绝缘体，DRAM中的电容器电介质，作为NROM电介质的闪存中的隧道栅极绝缘体，或其它电子器件中的电介质，因为高介电常数（高k）的膜提供了更薄的二氧化硅膜的功能。

9. 发明申请

US20130122609A1 Zr-SUBSTITUTED BaTiO3 FILMS 有权
标题翻译： Zr取代的BaTiO3膜
公开(公告)号：US20130122609A1
公开(公告)日：2013-05-16
申请号：US13692407
申请日：2012-12-03
申请人： Micron Technology, Inc.
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L43/12
CPC分类号： H01L21/02197 , C23C16/409 , C23C16/45529 , C23C16/45531 , H01L21/022 , H01L21/0228 , H01L21/02337 , H01L21/28194 , H01L21/28291 , H01L21/3142 , H01L21/31691 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/78 , H01L43/12 , H04L12/4625 , H04L45/02
摘要： The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide, produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. In various embodiments, structures can be formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. The properties of the dielectric may be tuned by adjusting the percentage of zirconium to titanium to optimize properties such as a dielectric constant, Curie point, film polarization, ferroelectric property and a desired relaxor response.
摘要翻译：使用单层或部分单层测序方法（例如原子层沉积（ALD））来形成锆钛氧化物的锆取代层，产生可靠的铁电结构，用于各种电子器件，例如非易失性介质随机存取存储器（NVRAM），多层陶瓷电容器（MLCC）的可调电介质，红外传感器和电光调制器。在各种实施方案中，可以通过使用前体化学品在基材表面上沉积钛酸钡和锆酸钡的交替层而形成结构，并重复形成所需厚度和组成的顺序沉积的交错结构。电介质的性质可以通过调整锆与钛的百分比来调节，以优化诸如介电常数，居里点，薄膜极化，铁电性能和期望的弛豫反应的性能。

10. 发明授权

US09893072B2 DRAM with nanofin transistors 有权
公开(公告)号：US09893072B2
公开(公告)日：2018-02-13
申请号：US14803954
申请日：2015-07-20
申请人： Micron Technology, Inc.
发明人： Leonard Forbes
IPC分类号： H01L27/108 , H01L21/02 , B82Y10/00 , H01L21/8234 , H01L29/78
CPC分类号： H01L27/10876 , B82Y10/00 , H01L21/02532 , H01L21/823487 , H01L27/10823 , H01L27/10826 , H01L27/10855 , H01L27/10879 , H01L29/785 , H01L2029/7858 , H01L2924/13067
摘要： One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

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