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51. 发明授权

US11450647B2 Semiconductor module and semiconductor device including the same 有权
公开(公告)号：US11450647B2
公开(公告)日：2022-09-20
申请号：US16776736
申请日：2020-01-30
申请人： DENSO CORPORATION
发明人： Takanori Kawashima
IPC分类号： H01L25/07 , H01L23/31 , H01L23/373 , H01L23/367 , H02P27/06
摘要： A semiconductor module disclosed herein may include: a first semiconductor element; an encapsulant that encapsulates the first semiconductor element; and a first stacked substrate on which the first semiconductor element is disposed, wherein the first stacked substrate may include a first insulator substrate, a first inner conductive layer and a first outer conductive layer, the first inner conductive layer being disposed on one side relative to the first insulator substrate, and the first outer conductive layer being disposed on another side relative to the first insulator substrate; the first inner conductive layer may be electrically connected to the first semiconductor element inside the encapsulant; and a part of the first inner conductive layer may be located outside the encapsulant and be configured to enable an external member to be bonded to the part.

52. 发明授权

US11444020B2 Via for semiconductor device connection and methods of forming the same 有权
公开(公告)号：US11444020B2
公开(公告)日：2022-09-13
申请号：US16846750
申请日：2020-04-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Wen-Chih Chiou , Tsang-Jiuh Wu , Der-Chyang Yeh , Ming Shih Yeh
IPC分类号： H01L23/522 , H01L21/768 , H01L21/033 , H01L21/311 , H01L21/3105 , H01L21/683 , H01L21/02 , H01L23/00 , H01L23/528 , H01L33/62 , H01L21/56 , H01L25/075 , H01L33/38 , H01L25/07 , H01L23/538 , H01L33/00 , H01L33/06 , H01L33/32 , H01L21/321
摘要： A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

53. 发明申请

US20220285325A1 PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME 有权
公开(公告)号：US20220285325A1
公开(公告)日：2022-09-08
申请号：US17751460
申请日：2022-05-23
申请人： Micron Technology, Inc.
发明人： Tongbi Jiang , Yong Poo Chia
IPC分类号： H01L25/07 , H01L25/00 , H01L23/31 , H01L23/48 , H01L21/768 , H01L21/82 , H01L23/00 , H01L21/56 , H01L23/538 , H01L25/10
摘要： A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

54. 发明授权

US11437311B2 Semiconductor module and method for producing the same 有权
公开(公告)号：US11437311B2
公开(公告)日：2022-09-06
申请号：US16951556
申请日：2020-11-18
申请人： Infineon Technologies AG
发明人： Olaf Hohlfeld , Peter Kanschat
IPC分类号： H01L21/00 , H01L23/498 , H01L23/367 , H01L23/40 , H01L23/31 , H01L23/24 , H01L21/56 , H01L25/07 , H01L23/00
摘要： A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.

55. 发明授权

US11431255B2 Analysis system, analysis method, and program storage medium 有权
公开(公告)号：US11431255B2
公开(公告)日：2022-08-30
申请号：US16634658
申请日：2018-08-02
申请人： NEC CORPORATION
发明人： Sangwon Hwang
IPC分类号： H02M7/00 , H04N5/232 , H04N5/247 , H01L23/50 , H01L23/52 , H01L25/07 , H01L25/18 , H01L27/06 , H01L27/07 , H01L29/66 , H01L25/11
摘要： In order to provide a feature for processing an image of an object being photographed using photographic data having better quality, an image analyzer 1 is provided with a selection unit 104 and a bandwidth control request unit 105. The selection unit 104 selects a second photographing device associated with a first photographing device from among a plurality of photographing devices. The bandwidth control request unit 105 transmits, to a network control device, a request for change of the transmission data amount transmittable by the second photographing device.

56. 发明申请

US20220271015A1 Structures for Providing Electrical Isolation in Semiconductor Devices 有权
公开(公告)号：US20220271015A1
公开(公告)日：2022-08-25
申请号：US17680437
申请日：2022-02-25
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Chan-Hong Chern , Mark Chen
IPC分类号： H01L25/07 , H01L25/00 , H01L23/00 , H01L23/498 , H01L21/48 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66 , H01L21/02
摘要： Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

57. 发明授权

US11417634B2 Semiconductor module having an N terminal, A P terminal and an output terminal and method of fabricating the semiconductor module 有权
公开(公告)号：US11417634B2
公开(公告)日：2022-08-16
申请号：US17033207
申请日：2020-09-25
申请人： FUJI ELECTRIC CO., LTD.
发明人： Motohito Hori , Yoshinari Ikeda
IPC分类号： H01L25/07 , H01L23/498 , H01L23/00 , H01L25/00
摘要： A semiconductor module having a first metal wiring board, a second metal wiring board, a third metal wiring board, and a first semiconductor element and a second semiconductor element that each include an emitter electrode and a collector electrode. The second metal wiring board is disposed over a principal surface of the first metal wiring board with an insulation material therebetween. The third metal wiring board has a principal surface thereof facing the first metal wiring board. The first and second semiconductor elements are disposed to face directions opposite to each other. The collector electrodes of the first and second semiconductor elements respectively face the principal surfaces of the first and third metal wiring boards. The emitter electrodes of the first and second semiconductor elements are respectively connected to the principal surfaces of the third and second metal wiring boards.

58. 发明授权

US11410970B2 Semiconductor module 有权
公开(公告)号：US11410970B2
公开(公告)日：2022-08-09
申请号：US16913524
申请日：2020-06-26
申请人： UltraMemory Inc.
发明人： Ryuji Takishita , Takao Adachi
IPC分类号： H01L25/065 , H01L23/367 , H01L23/498 , H01L23/00 , H01L25/04 , H01L25/07 , H01L25/11 , H01L27/02
摘要： The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.

59. 发明授权

US11410907B2 Semiconductor module 有权
公开(公告)号：US11410907B2
公开(公告)日：2022-08-09
申请号：US17216810
申请日：2021-03-30
申请人： FUJI ELECTRIC CO., LTD.
发明人： Tadahiko Sato
IPC分类号： H01L23/00 , H01L23/373 , H01L25/07 , H01L23/31
摘要： A semiconductor module includes a multilayer substrate having an insulating plate on which first to third conductive layers respectively connected to positive, negative and output electrode terminals are arranged in a first direction, a plurality of first semiconductor elements each having top and bottom electrodes on the first conductive layer and arranged in a second direction orthogonal to the first direction, a plurality of second semiconductor elements each having top and bottom electrodes on the second conductive layer and arranged in the second direction, first and second main wiring members each connecting the top electrode of each first and second semiconductor element to the second and third conductive layers. The multilayer substrate includes a first control wiring layer extending in the second direction and passing under the first main wiring member, and a second control wiring layer extending in the second direction and passing under the second main wiring member.

60. 发明授权

US11387187B2 Embedded very high density (VHD) layer 有权
公开(公告)号：US11387187B2
公开(公告)日：2022-07-12
申请号：US16021966
申请日：2018-06-28
申请人： Intel Corporation
发明人： Andrew Paul Collins , Jianyong Xie , Sujit Sharan , Henning Braunisch , Aleksandar Aleksov
IPC分类号： H01L23/495 , H01L23/053 , H01L23/48 , H01L21/4763 , H01L23/538 , H01L25/065 , H01L21/48 , H01L23/498 , H01L23/522 , H01L21/768 , H01L23/528 , H01L25/07
摘要： Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.

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