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51. 发明申请

US20130038380A1 IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK 有权
标题翻译：在TSV堆栈中进行芯片校准
公开(公告)号：US20130038380A1
公开(公告)日：2013-02-14
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： H03H11/00 , G06F17/50 , H01L29/68
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

52. 发明申请

US20110241760A1 CONTROL CIRCUIT, CONTROL DEVICE, CONTROL METHOD, AND IMAGE FORMING APPARATUS 有权
标题翻译：控制电路，控制装置，控制方法和图像形成装置
公开(公告)号：US20110241760A1
公开(公告)日：2011-10-06
申请号：US13040870
申请日：2011-03-04
申请人： Hiroyuki NAKAZAWA
发明人： Hiroyuki NAKAZAWA
IPC分类号： H03H11/00
CPC分类号： H03K19/017509 , H03K19/0016
摘要： A control circuit comprising an input-output unit that is connected to a signal line, which is connected to an external apparatus, and which is connected to a resistor that is one of a pull-up resistor and a pull-down resistor; a switching unit that switches a mode of the input-output unit to one of an input mode and an output mode, wherein the output mode includes an on-voltage output mode and an off-voltage output mode; an acquisition unit that acquires information regarding whether the resistor connected to the signal line is the pull-up resistor or the pull-down resistor, when the input-output unit is in the input mode; and a control unit that controls the input-output unit to switch to one of the on-voltage output mode and the off-voltage output mode based on the acquisition information acquired by the acquisition unit, when the input-output unit is in the output mode.
摘要翻译：一种控制电路，包括连接到与外部设备连接的信号线并且连接到作为上拉电阻器和下拉电阻器之一的电阻器的输入 - 输出单元; 切换单元，其将所述输入输出单元的模式切换为输入模式和输出模式之一，其中所述输出模式包括导通电压输出模式和截止电压输出模式; 获取单元，当输入输出单元处于输入模式时，获取关于连接到信号线的电阻器是上拉电阻器还是下拉电阻器的信息; 以及控制单元，当所述输入 - 输出单元处于所述输出单元中时，控制所述输入 - 输出单元基于所述获取单元获取的所述获取信息来切换到所述导通电压输出模式和所述截止电压输出模式中的一者模式。

53. 发明申请

US20110074499A1 SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME 失效
标题翻译：半导体器件及其控制方法
公开(公告)号：US20110074499A1
公开(公告)日：2011-03-31
申请号：US12891216
申请日：2010-09-27
申请人： Kazutoshi SAKO , Tomokazu Matsuzaki , Kouji Yokosawa
发明人： Kazutoshi SAKO , Tomokazu Matsuzaki , Kouji Yokosawa
IPC分类号： H03H11/00
CPC分类号： H03B5/32 , H03B5/36 , H03B2200/003 , H03B2200/006 , H03B2200/0062
摘要： A semiconductor device according to an exemplary aspect of the invention is capable of being selectively switched between an oscillation circuit and a signal input-output circuit, and includes first and second external connecting terminals that are connectable to an oscillation device; an inverting amplifier an input side of which is electrically connected to the first external connecting terminal through a coupling capacitor and an output side of which is electrically connected to the second external connecting terminal; a feedback resistor connected to the input side and the output side of the inverting amplifier; a bias stabilization circuit that stabilizes a bias applied to the coupling capacitor; a first signal input-output portion connected to the first external connecting terminal; and a second signal input-output portion connected to the second external connecting terminal.
摘要翻译：根据本发明的示例性方面的半导体器件能够在振荡电路和信号输入 - 输出电路之间选择性地切换，并且包括可连接到振荡器件的第一和第二外部连接端子; 反相放大器，其输入侧通过耦合电容器电连接到第一外部连接端子，并且其输出侧电连接到第二外部连接端子; 连接到反相放大器的输入侧和输出侧的反馈电阻器; 偏置稳定电路，稳定施加到耦合电容器的偏压; 连接到所述第一外部连接端子的第一信号输入 - 输出部分; 以及连接到第二外部连接端子的第二信号输入 - 输出部分。

54. 发明授权

US07683742B2 Integrated electronic circuitry comprising tunable resonator 有权
标题翻译：包括可调谐谐振器的集成电子电路
公开(公告)号：US07683742B2
公开(公告)日：2010-03-23
申请号：US11840137
申请日：2007-08-16
申请人： Andreia Cathelin , Stephane Razafimandimby , Cyrille Tilhac
发明人： Andreia Cathelin , Stephane Razafimandimby , Cyrille Tilhac
IPC分类号： H03H9/02 , H03H11/00 , H03B5/36
CPC分类号： H03J3/20 , H03H9/17 , H03H9/25
摘要： An electronic circuit includes: an acoustic resonator of BAW or SAW type, said resonator having a series resonance frequency and a parallel resonance frequency; an active circuit which is coupled in parallel to said acoustic resonator, said active circuit having a negative capacity acting on the parallel resonance frequency of said resonator.
摘要翻译：电子电路包括：具有BAW或SAW型的声共振器，所述谐振器具有串联谐振频率和并联谐振频率; 与所述声谐振器并联耦合的有源电路，所述有源电路具有作用在所述谐振器的并联谐振频率上的负电容。

55. 发明申请

US20090289694A1 Current-Sensing Apparatus and Method for Current Sensing 审中-公开
标题翻译：电流检测装置及电流检测方法
公开(公告)号：US20090289694A1
公开(公告)日：2009-11-26
申请号：US12309488
申请日：2007-07-24
申请人： Gotthard Rieger , Richard Schmidt , Roland Weiss
发明人： Gotthard Rieger , Richard Schmidt , Roland Weiss
IPC分类号： G01R17/22 , G01R1/20 , H03H11/00 , G01R33/09
CPC分类号： G01R15/205
摘要： At least one embodiment of the invention specifies a current-sensing apparatus and/or a method for its operation which is based on the current sensor provided being a GMR sensor in the form of a gradient sensor and on the gradient sensor, or a component which includes this gradient sensor, itself including a conductor section of a compensating circuit. As such, the current in the measurement circuit can be compensated for by a current in the compensating circuit and the compensating current can be evaluated as a measure of the electrical variable to be detected for the measurement circuit.
摘要翻译：本发明的至少一个实施例规定了一种电流感测装置和/或其操作方法，其基于提供的梯度传感器形式的GMR传感器和梯度传感器所提供的电流传感器，包括该梯度传感器，其本身包括补偿电路的导体部分。因此，可以通过补偿电路中的电流补偿测量电路中的电流，并且可以将补偿电流评估为测量电路要检测的电变量的量度。

56. 发明申请

US20080169794A1 Systems for providing a constant resistance 有权
标题翻译：提供恒定电阻的系统
公开(公告)号：US20080169794A1
公开(公告)日：2008-07-17
申请号：US11653037
申请日：2007-01-12
申请人： Vijaya B. Rentala , Baher Haroun
发明人： Vijaya B. Rentala , Baher Haroun
IPC分类号： H03H11/46 , H03H11/00 , G05F1/46
CPC分类号： H03H11/24
摘要： A system for providing a desired substantially constant resistance includes a first transistor interconnected between a first node and a second node. The system also includes a second transistor, the second transistor being diode connected, the first transistor and the second transistor forming a current mirror. A voltage divider is coupled to provide a portion of a voltage associated with the first transistor to the second transistor, the voltage divider being configured parallel to the first transistor to provide a substantially constant resistance between the first node and the second node. A current source is coupled to the second transistor, the current source being controlled to draw an amount of current through the second transistor to set the substantially constant resistance substantially equal to the desired substantially constant resistance.
摘要翻译：用于提供期望的基本上恒定的电阻的系统包括在第一节点和第二节点之间互连的第一晶体管。该系统还包括第二晶体管，第二晶体管被二极管连接，第一晶体管和第二晶体管形成电流镜。耦合分压器以将与第一晶体管相关联的电压的一部分提供给第二晶体管，该分压器被配置成与第一晶体管并联，以在第一节点和第二节点之间提供基本恒定的电阻。电流源耦合到第二晶体管，电流源被控制以画出通过第二晶体管的电流量，以将基本上恒定的电阻设置为基本上等于期望的基本上恒定的电阻。

57. 发明申请

US20080048760A1 Monolithically integratable circuit arrangement 失效
标题翻译：单片可积分电路布置
公开(公告)号：US20080048760A1
公开(公告)日：2008-02-28
申请号：US11882113
申请日：2007-07-30
申请人： Samir El Rai , Ralf Tempel
发明人： Samir El Rai , Ralf Tempel
IPC分类号： H03H11/00
CPC分类号： H01L27/08 , H01F27/34 , H01F27/402 , H01F2017/002 , H01F2017/0046 , H01L23/5223 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H03B5/1841 , H01L2924/00
摘要： A monolithically integratable circuit arrangement is provided, which has at least one inductor, formed as a conductor loop, and at least one capacitor, connected to the conductor loop. According to the invention, the circuit arrangement comprises (a) at least one first conductor loop placed in at least one first metallization level and having a first DC terminal for applying a first DC potential, (b) at least one second conductor loop placed in at least one second metallization level and having a second DC terminal for applying a second DC potential, (c) at least one metal-isolator-metal capacitor with a capacitor plate, which is placed in a third metallization level between the first and second metallization level, and (d) at least one metallic connecting means placed between the capacitor plate and the first conductor loop, said means which connects the capacitor plate in an electrically conducting manner to the first conductor loop. The invention relates furthermore to an integrated circuit having a circuit arrangement of this type.
摘要翻译：提供了一种单片可积分电路装置，其具有形成为导体环路的至少一个电感器和连接到导体环路的至少一个电容器。根据本发明，电路装置包括（a）放置在至少一个第一金属化电平中的至少一个第一导体环路，并具有用于施加第一DC电位的第一DC端子，（b）至少一个第二导体环路，至少一个第二金属化水平并且具有用于施加第二DC电位的第二DC端子，（c）至少一个具有电容器板的金属隔离金属电容器，其被放置在第一和第二金属化之间的第三金属化水平以及（d）放置在电容器板和第一导体环之间的至少一个金属连接装置，所述装置将电容器板以导电方式连接到第一导体环路。本发明还涉及具有这种类型的电路装置的集成电路。

58. 发明申请

US20080001683A1 INTEGRATED CIRCUIT INCORPORATING WIRE BOND INDUCTANCE 有权
标题翻译：集成电路并入线束电感
公开(公告)号：US20080001683A1
公开(公告)日：2008-01-03
申请号：US11548516
申请日：2006-10-11
申请人： James Wight , Johan Grundlingh
发明人： James Wight , Johan Grundlingh
IPC分类号： H03H7/38 , H03H11/00 , H03H7/00
CPC分类号： H01L23/66 , H01L23/3128 , H01L23/5227 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/16 , H01L2224/45014 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01014 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack. a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die.
摘要翻译：本发明涉及电子领域，更具体地说，涉及结合到集成电路封装中的引线键合，例如四方扁平封装，球栅阵列或混合型模块。本发明采用通常不期望的接线电感，并将其用于需要正电感的运算电路中。使用引线键合电感的电路主要位于集成电路封装中的集成电路管芯中，但也可以包括脱模组件。在一个示例中，在由两个并联对地负电感和一个串联正电感组成的分立电路阻抗逆变器中，使用引线键作为所需的串联电感。负电感器之一位于管芯上，而另一个位于裸片上。

59. 发明申请

US20070257748A1 ACTIVE INDUCTOR 审中-公开
标题翻译：主动电感器
公开(公告)号：US20070257748A1
公开(公告)日：2007-11-08
申请号：US11738161
申请日：2007-04-20
申请人： Kazuo Kawai
发明人： Kazuo Kawai
IPC分类号： H03H11/00
CPC分类号： H03H11/48
摘要： The present invention provides an active inductor comprising an input terminal, a primary all-pass type 90° phase-delayed stage constituted of discrete elements, and a phase inversion amplifying stage and including a constitution in which a signal supplied to the input terminal is inputted to the primary all-pass type 90° phase-delayed stage, a 90° phase-delayed signal obtained at its output is inputted to the phase inversion amplifying stage subsequent to the primary all-pass type 90° phase-delayed stage and phase-inversion amplified thereat, and an output produced from the phase inversion amplifying stage is feedback-coupled to the input terminal. The resistance value of a load resistor of the phase inversion amplifying stage is adjusted in such a manner that the signal gain between an input end of the primary all-pass type 90° phase-delayed stage and an output end of the phase inversion amplifying stage is brought to 1, whereby the active inductor is configured so as to exhibit an equivalent inductor when the inside of the active inductor is seen from the input terminal.
摘要翻译：本发明提供一种有源电感器，其包括输入端子，由分立元件构成的初级全通型90°相位延迟级和相位反转放大级，并且包括其中输入到输入端子的信号被输入的结构到初级全通型90°相位延迟级，在其输出处获得的90°相位延迟信号被输入到初级全通型90°相位延迟级和相位延迟级之后的相位反转放大级，反相放大，从相位反转放大级产生的输出反馈耦合到输入端。调整相位反转放大级的负载电阻的电阻值，使得初级全通型90°相位延迟级的输入端与相位反相放大级的输出端之间的信号增益被置为1，由此，当从输入端看到有源电感器的内部时，有源电感器被配置为呈现等效的电感器。

60. 发明申请

US20070257747A1 ACTIVE CAPACITOR 审中-公开
标题翻译：主动电容器
公开(公告)号：US20070257747A1
公开(公告)日：2007-11-08
申请号：US11738065
申请日：2007-04-20
申请人： Kazuo Kawai
发明人： Kazuo Kawai
IPC分类号： H03H11/00
CPC分类号： H03H11/481
摘要： The present invention provides an active capacitor comprising an input terminal, a primary all-pass type 90° phase-advanced stage constituted of discrete elements, and a phase inversion amplifying stage and including a constitution in which a signal supplied to the input terminal is inputted to the primary all-pass type 90° phase-advanced stage, a 90° phase-advanced signal obtained at its output is inputted to the phase inversion amplifying stage subsequent to the primary all-pass type 90° phase-advanced stage and phase-inversion amplified thereat, and an output produced from the phase inversion amplifying stage is feedback-coupled to the input terminal. The resistance value of a load resistor of the phase inversion amplifying stage is adjusted in such a manner that the signal gain between an input end of the primary all-pass type 90° phase-advanced stage and an output end of the phase inversion amplifying stage is brought to 1, whereby the active capacitor is configured so as to exhibit an equivalent capacitor when the inside of the circuit is seen from the input terminal.
摘要翻译：本发明提供一种有源电容器，其包括输入端子，由分立元件构成的初级全通型90°相位超前级和相位反转放大级，并且包括输入到输入端子的信号被输入的结构在初级全通型90°相位提前级中，在其输出端获得的90°相位超前信号被输入到初级全通型90°相位超前级和相位超前级之后的相位反转放大级，反相放大，从相位反转放大级产生的输出反馈耦合到输入端。调整相位反转放大级的负载电阻的电阻值，使得初级全通型90°相位提前级的输入端与相位反相放大级的输出端之间的信号增益使其为1，由此，从输入端子看到电路的内部，有源电容器被构造为呈现等效的电容器。

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