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1. 发明授权

US09086957B2 Requesting a memory space by a memory controller 有权
标题翻译：通过内存控制器请求内存空间
公开(公告)号：US09086957B2
公开(公告)日：2015-07-21
申请号：US13565503
申请日：2012-08-02
申请人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06F3/06 , G06F11/22 , G06F12/08
CPC分类号： G06F12/0292 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F11/2221 , G06F12/00 , G06F12/0223 , G06F12/0646 , G06F12/0802 , Y02D10/13
摘要： Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.
摘要翻译：提供系统和方法来处理来自存储器控制器的存储器空间的请求。特定方法可以包括由存储器控制器向计算机程序传送对存储器的存储器空间的请求。存储器控制器被配置为初始化存储器，并且存储器控制器被配置为按照指示对存储器执行操作。计算机程序被配置为使存储器的存储器空间响应于对存储器的存储器空间的请求而可用。该方法还可以包括响应于来自计算机程序的指示使存储器空间可用的存储器空间。还提供了用于在存储器控制器的独占控制下将存储器控制器的存储器空间复制到存储器空间的系统和方法。

2. 发明授权

US08869007B2 Three dimensional (3D) memory device sparing 有权
标题翻译：三维（3D）存储设备备用
公开(公告)号：US08869007B2
公开(公告)日：2014-10-21
申请号：US13523091
申请日：2012-06-14
申请人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
发明人： Edgar R. Cordero , Anil B. Lingambudi , Saravanan Sethuraman , Kenneth L. Wright
IPC分类号： G11C29/00 , G06F11/10 , G11C29/44 , H03M13/05
CPC分类号： G06F11/1072 , G06F11/1048 , G11C5/04 , G11C11/40 , G11C29/4401 , G11C29/886 , G11C2029/0409 , H03M13/05
摘要： According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
摘要翻译：根据本发明的一个实施例，一种用于操作三维（“3D”）存储器件的方法包括由存储器控制器检测3D存储器件上的第一个错误，并由存储器控制器检测第二个错误在3D存储器件的第一级中的第一芯片中，其中第一芯片具有相关的第一芯片选择。该方法还包括对第二级别的第二芯片供电，从存储器控制器向3D存储器件发送命令以将第一芯片中的第一芯片替换为第二芯片，并使用错误控制代码校正第一错误。

3. 发明授权

US08692561B2 Implementing chip to chip calibration within a TSV stack 有权
标题翻译：在TSV堆栈内实现芯片到芯片校准
公开(公告)号：US08692561B2
公开(公告)日：2014-04-08
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： G01R35/00
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

4. 发明申请

US20140040576A1 REQUESTING A MEMORY SPACE BY A MEMORY CONTROLLER 有权
标题翻译：由记忆控制器请求记忆空间
公开(公告)号：US20140040576A1
公开(公告)日：2014-02-06
申请号：US13565503
申请日：2012-08-02
申请人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
发明人： Edgar R. Cordero , Robert B. Tremaine , Varkey Kalloorthazchayil Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F12/16
CPC分类号： G06F12/0292 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F11/2221 , G06F12/00 , G06F12/0223 , G06F12/0646 , G06F12/0802 , Y02D10/13
摘要： Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.
摘要翻译：提供系统和方法来处理来自存储器控制器的存储器空间的请求。特定方法可以包括由存储器控制器向计算机程序传送对存储器的存储器空间的请求。存储器控制器被配置为初始化存储器，并且存储器控制器被配置为按照指示对存储器执行操作。计算机程序被配置为使存储器的存储器空间响应于对存储器的存储器空间的请求而可用。该方法还可以包括响应于来自计算机程序的指示使存储器空间可用的存储器空间。还提供了用于在存储器控制器的独占控制下将存储器控制器的存储器空间复制到存储器空间的系统和方法。

5. 发明申请

US20130038380A1 IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK 有权
标题翻译：在TSV堆栈中进行芯片校准
公开(公告)号：US20130038380A1
公开(公告)日：2013-02-14
申请号：US13207688
申请日：2011-08-11
申请人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
发明人： Edgar R. Cordero , Divya Kumar , Anuwat Saetow , Robert B. Tremaine
IPC分类号： H03H11/00 , G06F17/50 , H01L29/68
CPC分类号： G06F1/10 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
摘要翻译：一种用于在芯片堆栈中实现芯片到芯片校准的方法和电路，例如通过硅通孔（TSV）堆叠以及设置有被摄体电路所在的设计结构。第一芯片和第二芯片包括在半导体芯片堆叠内。半导体芯片堆叠包括可选地设置有芯片的通过硅通道（TSV）堆叠的垂直堆叠。第一芯片和第二芯片中的至少一个包括校准控制电路和耦合到校准控制电路的性能指示器电路，以训练和校准第一芯片和第二芯片中的至少一个以提供增强的性能和可靠性半导体芯片堆栈。

6. 发明授权

US07571357B2 Memory wrap test mode using functional read/write buffers 失效
标题翻译：内存包装测试模式使用功能读/写缓冲区
公开(公告)号：US07571357B2
公开(公告)日：2009-08-04
申请号：US11466111
申请日：2006-08-22
申请人： Mark A. Brittain , Edgar R. Cordero , John T. Hollaway, Jr. , Eric E. Retter
发明人： Mark A. Brittain , Edgar R. Cordero , John T. Hollaway, Jr. , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G01R31/31722 , G01R31/31712 , G11C29/48
摘要： A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.
摘要翻译：用于处理单元的存储器控制器提供存储器包裹测试模式路径，其选择性地将数据从控制器的写入缓冲器写入到控制器的读取缓冲器，从而允许写入和读取缓冲器在测试期间替换系统存储器件处理单元。因此，处理单元可以在没有附加的存储器件的情况下进行测试，但仍然在产生与实际（最终使用）操作下生成的总线流量和芯片噪声类似的条件下操作。当处理器在测试模式下发出写入操作时，控制器将数据写入对应于写入地址的读取缓冲器的条目。此后，处理器可以发出具有相同地址的读取操作，并且读取缓冲器将从相应的条目发送数据。

7. 发明申请

US20080215929A1 SWITCHING A DEFECTIVE SIGNAL LINE WITH A SPARE SIGNAL LINE WITHOUT SHUTTING DOWN THE COMPUTER SYSTEM 失效
标题翻译：切换带有备用信号线的有缺陷的信号线，而不需要切断计算机系统
公开(公告)号：US20080215929A1
公开(公告)日：2008-09-04
申请号：US12098294
申请日：2008-04-04
申请人： Edgar R. Cordero , James S. Fields , Kevin C. Gower , Eric E. Retter
发明人： Edgar R. Cordero , James S. Fields , Kevin C. Gower , Eric E. Retter
IPC分类号： G06F11/00
CPC分类号： G06F11/10 , G06F11/2007 , G11C29/025 , G11C2029/0409
摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.
摘要翻译：一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

8. 发明授权

US09063902B2 Implementing enhanced hardware assisted DRAM repair using a data register for DRAM repair selectively provided in a DRAM module 有权
标题翻译：在DRAM模块中选择性地提供使用用于DRAM修复的数据寄存器来实现增强的硬件辅助DRAM修复
公开(公告)号：US09063902B2
公开(公告)日：2015-06-23
申请号：US13343938
申请日：2012-01-05
申请人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
发明人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G06F11/18 , G06F11/16 , G11C29/00 , G06F11/10 , G06F11/20 , G06F11/14
CPC分类号： G06F11/1666 , G06F11/1048 , G06F11/141 , G06F11/20 , G11C29/76
摘要： A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.
摘要翻译：提供了一种在支持ECC的计算机系统中实现硬件辅助动态随机存取存储器（DRAM）修复的方法，系统和计算机程序产品。提供DRAM修复的数据寄存器被选择性地提供在动态随机存取存储器（DRAM），存储器控制器或耦合在DRAM和存储器控制器之间的存储缓冲器之一中。数据寄存器被配置为映射到任何地址。响应于所检测到的配置地址，从配置的地址的读取或写入路由到数据寄存器。

9. 发明申请

US20140068322A1 IIMPLEMENTING DRAM COMMAND TIMING ADJUSTMENTS TO ALLEVIATE DRAM FAILURES 有权
标题翻译：将DRAM命令定时调整到可靠的DRAM故障
公开(公告)号：US20140068322A1
公开(公告)日：2014-03-06
申请号：US13598072
申请日：2012-08-29
申请人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
发明人： Edgar R. Cordero , Joab D. Henderson , Divya Kumar , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G06F11/14
CPC分类号： G11C29/023 , G06F11/073 , G06F11/0793 , G06F13/1689 , G11C11/40 , G11C29/028 , G11C29/44
摘要： A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.
摘要翻译：提供了一种用于实现命令定时调整以减轻计算机系统中的动态随机存取存储器（DRAM）故障的方法，系统和计算机程序产品。检测到预定义的DRAM故障。响应于检测到的故障，调整一组定时器以控制用于访问DRAM的预定定时。响应于通过调整的定时器组来解决故障，执行预定的性能水平的检查。

10. 发明申请

US20140063987A1 MEMORY OPERATION UPON FAILURE OF ONE OF TWO PAIRED MEMORY DEVICES 有权
公开(公告)号：US20140063987A1
公开(公告)日：2014-03-06
申请号：US13597926
申请日：2012-08-29
申请人： Edgar R. Cordero , Timothy J. Dell , Girisankar Paulraj , Saravanan Sethuraman
发明人： Edgar R. Cordero , Timothy J. Dell , Girisankar Paulraj , Saravanan Sethuraman
IPC分类号： G11C7/00
CPC分类号： G11C29/04 , G06F13/1673 , G11C29/70 , G11C29/808 , G11C2029/0411
摘要： A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.

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