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61. 发明授权

US07245534B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07245534B2
公开(公告)日：2007-07-17
申请号：US11135415
申请日：2005-05-24
申请人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
发明人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

62. 发明申请

US20070140036A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070140036A1
公开(公告)日：2007-06-21
申请号：US11678632
申请日：2007-02-26
申请人： Mitsuhiro NOGUCHI , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro NOGUCHI , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C7/00
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.
摘要翻译：半导体存储器件包括：存储单元阵列，具有彼此平行布置的多个数据选择线;多个数据传输线，彼此并联设置，以与数据选择线相交;以及布置的电可重写存储器单元在数据选择线和数据传输线之间的交叉部分; 用于驱动存储单元阵列的数据选择线的数据选择线驱动器; 连接到存储单元阵列的数据传输线的读出放大器电路，用于对数据选择线之一选择的存储器单元执行数据读取; 以及用于对存储单元阵列的数据读取进行定时控制的控制电路，用于根据存储单元阵列的选定数据区输出不同的至少两种类型的定时信号。

63. 发明申请

US20070047327A1 Erase method for flash memory 审中-公开
标题翻译：闪存的擦除方法
公开(公告)号：US20070047327A1
公开(公告)日：2007-03-01
申请号：US11215940
申请日：2005-08-31
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C8/08 , G11C16/08 , G11C16/107 , G11C16/3472
摘要： A non-volatile memory device and programming process is described that erases blocks of non-volatile memory cells by the application of differing word line erase voltages to selected word lines during an erase cycle. This facilitates for a faster on average erase operation, a tighter erased cell Vt distribution, an increase in memory device endurance and lifetimes due to a decrease in memory cell overerasure and overstress, and a more accurate match of word line voltages to the specific non-volatile memory array, the specific region or row being programmed, and any changes in programming characteristics due to device use and wear. In one embodiment of the present invention, the differing word line erase voltages are utilized to compensate for faster and slower erasing word lines. In another embodiment, different word line erase voltages are applied based on physical aspects of the word lines of the array.
摘要翻译：描述了非易失性存储器件和编程过程，其通过在擦除周期期间将不同的字线擦除电压施加到所选择的字线来擦除非易失性存储器单元的块。这有助于更快的平均擦除操作，更严格的擦除单元Vt分布，由于存储器单元过度和过应力的降低而导致的存储器件耐久性和寿命增加，以及字线电压与特定非线性电压的更准确的匹配，易失性存储器阵列，正在编程的特定区域或行，以及由于器件使用和磨损而导致的编程特性的任何变化。在本发明的一个实施例中，利用不同的字线擦除电压来补偿更快和更慢的擦除字线。在另一个实施例中，基于阵列的字线的物理方面来应用不同的字线擦除电压。

64. 发明申请

US20060268608A1 Data storage system 失效
公开(公告)号：US20060268608A1
公开(公告)日：2006-11-30
申请号：US11497325
申请日：2006-08-02
申请人： Mitsuhiro Noguchi , Akira Goda
发明人： Mitsuhiro Noguchi , Akira Goda
IPC分类号： G11C16/06
CPC分类号： G06F11/1008 , G11C16/0483
摘要： A data storage system, which includes a plurality of pages, each of which includes a plurality of first memory cells, from which at least binary data can be read-out a plurality of times without destruction; a circuit which receives data-output of at least one first page, detects an error in at least one bit of data, and outputs information of the error position; another circuit which determines whether data of an error bit is “1” or “0”. When the determination is “1” or “0”, the first memory cell of the first page is erased, and error-corrected data is written.

65. 发明授权

US07057936B2 Nonvolatile semiconductor memory device 失效
公开(公告)号：US07057936B2
公开(公告)日：2006-06-06
申请号：US10896081
申请日：2004-07-22
申请人： Toshitake Yaegashi , Akira Goda , Mitsuhiro Noguchi
发明人： Toshitake Yaegashi , Akira Goda , Mitsuhiro Noguchi
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C16/3468
摘要： A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.

66. 发明授权

US06969660B2 Method of manufacturing a semiconductor device with trench isolation between two regions having different gate insulating films 失效
标题翻译：在具有不同栅极绝缘膜的两个区域之间制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US06969660B2
公开(公告)日：2005-11-29
申请号：US11007462
申请日：2004-12-09
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
IPC分类号： H01L27/115 , H01L21/762 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11573
摘要： The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.
摘要翻译：半导体器件的半导体衬底的主表面包括第一和第二区域以及它们之间的边界区域。第一栅极绝缘膜和第一栅电极形成在第一区域中。在第二区域中形成与第一栅极绝缘膜和第二栅极电极不同的第二栅极绝缘膜。在边界区域形成器件隔离区。该器件隔离区域包括形成在主表面中的沟槽，以及绝缘层，其具有埋在沟槽中的部分和从主表面向上突出的部分。沟槽的底部具有与部分不同的深度。

67. 发明授权

US06943453B2 Superconductor device and method of manufacturing the same 失效
公开(公告)号：US06943453B2
公开(公告)日：2005-09-13
申请号：US10318257
申请日：2002-12-13
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792 , H01L29/40
CPC分类号： H01L27/11568 , H01L21/76838 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.

68. 发明申请

US20050141291A1 Semiconductor memory 有权
公开(公告)号：US20050141291A1
公开(公告)日：2005-06-30
申请号：US11068228
申请日：2005-03-01
申请人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
发明人： Mitsuhiro Noguchi , Akira Goda , Yasuhiko Matsunaga
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/26 , G11C16/0483 , H01L27/115
摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

69. 发明申请

US20050133874A1 Method of manufactoring a semiconductor device with trench isolation between two regions having different gate insulating films 失效
标题翻译：在具有不同栅极绝缘膜的两个区域之间制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US20050133874A1
公开(公告)日：2005-06-23
申请号：US11007462
申请日：2004-12-09
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
IPC分类号： H01L27/115 , H01L21/762 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11568 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11573
摘要： The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.
摘要翻译：半导体器件的半导体衬底的主表面包括第一和第二区域以及它们之间的边界区域。第一栅极绝缘膜和第一栅电极形成在第一区域中。在第二区域中形成与第一栅极绝缘膜和第二栅极电极不同的第二栅极绝缘膜。在边界区域形成器件隔离区。该器件隔离区域包括形成在主表面中的沟槽，以及绝缘层，其具有埋在沟槽中的部分和从主表面向上突出的部分。沟槽的底部具有与部分不同的深度。

70. 发明授权

US06882592B2 Semiconductor memory device 失效
公开(公告)号：US06882592B2
公开(公告)日：2005-04-19
申请号：US10696028
申请日：2003-10-30
申请人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro Noguchi , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C16/02 , G06F11/10 , G11C8/00 , G11C11/34 , G11C16/00 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/42 , G11C29/52 , H01L21/8247 , H01L27/00 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.

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