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61. 发明申请

US20150347140A1 PROCESSOR THAT LEAPFROGS MOV INSTRUCTIONS 有权
标题翻译：处理器可以使用说明书
公开(公告)号：US20150347140A1
公开(公告)日：2015-12-03
申请号：US14315122
申请日：2014-06-25
申请人： VIA TECHNOLOGIES, INC.
发明人： Gerard M. Col , Matthew Daniel Day
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30069 , G06F9/30032 , G06F9/384 , G06F9/3855
摘要： A processor performs out-of-order execution of a first instruction and a second instruction after the first instruction in program order, the first instruction includes source and destination indicators, the source indicator specifies a source of data, the destination indicator specifies a destination of the data, the first instruction instructs the processor to move the data from the source to the destination, the second instruction specifies a source indicator that specifies a source of data. A rename unit updates the second instruction source indicator with the first instruction source indicator if there are no intervening instructions that write to the source or to the destination of the first instruction and the second instruction source indicator matches the first instruction destination indicator.
摘要翻译：处理器以程序顺序执行在第一指令之后的第一指令和第二指令的无序执行，第一指令包括源和目标指示符，源指示符指定数据源，目的地指示符指定数据，第一指令指示处理器将数据从源移动到目的地，第二指令指定指定数据源的源指示符。如果没有写入到第一指令的源或目的地的第二指令源指示符，并且第二指令源指示符与第一指令目标指示符匹配，则重命名单元用第一指令源指示符更新第二指令源指示符。

62. 发明授权

US09197454B2 Differential signal transmitters 有权
标题翻译：差分信号发射机
公开(公告)号：US09197454B2
公开(公告)日：2015-11-24
申请号：US14156700
申请日：2014-01-16
申请人： VIA TECHNOLOGIES, INC.
发明人： Chun-Che Huang
IPC分类号： H04L27/00 , H04L25/02
CPC分类号： H04L25/0272 , H04L25/029
摘要： A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.
摘要翻译：差分信号发送器电路包括输出驱动电路和漏电流防止电路。输出驱动器电路被配置为根据电源发送一对差分信号。泄漏电流防止电路耦合到电源并且被配置为将电源电力耦合到处于通电状态的输出驱动器电路，并且在断电状态下将输出驱动器电路的电源解耦。

63. 发明申请

US20150324283A1 FLASH MEMORY CONTROL CHIP AND DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD 有权
标题翻译：闪存存储器控制芯片和数据存储设备和闪速存储器控制方法
公开(公告)号：US20150324283A1
公开(公告)日：2015-11-12
申请号：US14469703
申请日：2014-08-27
申请人： VIA TECHNOLOGIES, INC.
发明人： Yi-Lin LAI
IPC分类号： G06F12/02 , G11C29/42 , G11C29/52 , G06F11/10
CPC分类号： G06F3/06 , G06F11/1072 , G06F12/0246 , G06F12/06 , G06F2212/7201 , G11C29/42 , G11C29/52
摘要： A flash memory control method, storing a logical-to-physical address mapping relationship between a host and a flash memory and a root table in the flash memory and providing a non-volatile storage area storing a root table pointer. A mapping relationship pointer is set forth in the root table to show where the logical-to-physical address mapping relationship is stored in the flash memory. The root table pointer points to the root table stored in the flash memory. In response to a power restoration request issued from the host, the flash memory is accessed based on the root table pointer and thereby the root table is read and the logical-to-physical address mapping relationship is retrieved from the flash memory based on the mapping relationship pointer set forth in the root table.
摘要翻译：一种闪速存储器控制方法，存储主机与闪速存储器之间的逻辑到物理地址映射关系以及闪速存储器中的根表，并提供存储根表指针的非易失性存储区域。映射关系指针在根表中列出，以显示逻辑到物理地址映射关系存储在闪存中的位置。根表指针指向存储在闪存中的根表。响应从主机发出的电源恢复请求，基于根表指针访问闪存，从而读取根表，并且基于映射从闪存中检索逻辑到物理地址映射关系关系指针在根表中列出。

64. 发明授权

US09142541B2 Semiconductor device having inductor 有权
标题翻译：具有电感器的半导体器件
公开(公告)号：US09142541B2
公开(公告)日：2015-09-22
申请号：US14076419
申请日：2013-11-11
申请人： VIA TECHNOLOGIES, INC.
发明人： Sheng-Yuan Lee
IPC分类号： H01L27/02 , H01L23/522
CPC分类号： H01L28/10 , H01L23/5227 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines.
摘要翻译：公开了一种包括顺序地设置在基板上的第一绝缘层和第二绝缘层的半导体器件。第一导电线和第二导线设置在第一绝缘层中，并且第一和第二导线中的每一个具有第一端和第二端，其中第一和第二导线的第二端耦合到每个其他。第一绕组部分和第二绕组部分设置在第二绝缘层中，并且第一和第二绕组部分中的每一个包括从内向外布置的第三导线和第四导线。第三和第四导线中的每一个具有第一端和第二端，其中第一和第二导线与第三导线的至少一部分重叠。

65. 发明申请

US20150254093A1 SYSTEM AND METHOD FOR ASSIGNING VIRTUAL FUNCTIONS AND MANAGEMENT HOST THEREOF 有权
标题翻译：用于分配虚拟功能和管理的系统和方法
公开(公告)号：US20150254093A1
公开(公告)日：2015-09-10
申请号：US14267931
申请日：2014-05-02
申请人： VIA Technologies, Inc.
发明人： Kuan-Jui Ho
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/45579
摘要： A system and a method for assigning virtual functions, and a management host thereof are provided. The management host is connected with a computer host through a bridge and has at least one virtual function. A management processor of the management host updates a mapping table according to a virtual function establishing request to assign the at least one virtual function to the computer host according to the mapping table, wherein the management processor determines whether to establish the virtual function according to the mapping table. The management processor transmits a hot-plug event to the corresponding computer host via a switch according to an assignment result and connects the virtual function with the corresponding computer host to dynamically adjust an allocation of the virtual function.
摘要翻译：提供了一种用于分配虚拟功能的系统和方法及其管理主机。管理主机通过网桥连接到计算机主机，并具有至少一个虚拟功能。管理主机的管理处理器根据虚拟功能建立请求更新映射表，以根据映射表将至少一个虚拟功能分配给计算机主机，其中管理处理器根据该映射表确定是否建立虚拟功能映射表。管理处理器根据分配结果经由交换机向对应的计算机主机发送热插拔事件，并将虚拟功能与相应的计算机主机相连接以动态地调整虚拟功能的分配。

66. 发明授权

US09118308B1 Duty cycle corrector 有权
标题翻译：占空比校正器
公开(公告)号：US09118308B1
公开(公告)日：2015-08-25
申请号：US14175220
申请日：2014-02-07
申请人： VIA TECHNOLOGIES, INC.
发明人： Yeong-Sheng Lee
IPC分类号： H03K5/156 , H03K3/017
CPC分类号： H03K3/017 , H03K5/1565
摘要： A duty cycle corrector includes a VCD (Voltage-Controlled Delay) circuit, an edge detector, an SR latch, a mode controller, and a CP (Charge Pump) circuit. The VCD circuit delays an input clock signal for a delay period so as to generate a delay clock signal. The delay period is adjusted according to a CP control voltage. The edge detector detects clock edges of the input clock signal and the delay clock signal so as to correspondingly generate a first clock edge signal and a second clock edge signal. The SR latch generates a toggling signal according to the first clock edge signal and the second clock edge signal. The mode controller generates a mode control voltage. The CP circuit operates in different modes according to the mode control voltage. The CP circuit generates the CP control voltage according to the toggling signal and the mode control voltage.
摘要翻译：占空比校正器包括VCD（电压控制延迟）电路，边缘检测器，SR锁存器，模式控制器和CP（电荷泵）电路。 VCD电路将输入时钟信号延迟延迟时间，以产生延迟时钟信号。根据CP控制电压调整延迟时间。边沿检测器检测输入时钟信号和延迟时钟信号的时钟沿，以便相应地产生第一时钟沿信号和第二时钟沿信号。 SR锁存器根据第一时钟沿信号和第二时钟沿信号产生切换信号。模式控制器产生模式控制电压。 CP电路根据模式控制电压工作在不同的模式。 CP电路根据切换信号和模式控制电压产生CP控制电压。

67. 发明授权

US09116825B2 Memory controller 有权
标题翻译：内存控制器
公开(公告)号：US09116825B2
公开(公告)日：2015-08-25
申请号：US13910138
申请日：2013-06-05
申请人： VIA Technologies, Inc.
发明人： Ming-Han Chung
IPC分类号： H03M13/00 , G06F11/10 , H03M13/11
CPC分类号： G06F11/10 , H03M13/1117 , H03M13/116 , H03M13/616 , H03M13/6502
摘要： A memory controller is provided. The memory controller includes a memory interface and an encoding module. The memory interface is configured to couple to a memory chip. The encoding module is coupled to the memory interface and includes a shared memory and a parity generation module. The parity generation module is coupled to the shared memory. The parity generation module reads at least one basic vector from the shared memory, determines a dimension of the at least one basic vector, generates a generation matrix according to the at least one basic vector, converts a raw data into a codeword through the generation matrix, and stores the codeword into the memory chip through the memory interface.
摘要翻译：提供存储器控制器。存储器控制器包括存储器接口和编码模块。存储器接口被配置为耦合到存储器芯片。编码模块耦合到存储器接口并且包括共享存储器和奇偶生成模块。奇偶生成模块耦合到共享存储器。奇偶校验生成模块从共享存储器读取至少一个基本向量，确定至少一个基本向量的维度，根据至少一个基本向量生成生成矩阵，通过生成矩阵将原始数据转换为码字，并通过存储器接口将码字存储到存储器芯片中。

68. 发明授权

US09111752B1 Electrostatic discharge protection device 有权
标题翻译：静电放电保护装置
公开(公告)号：US09111752B1
公开(公告)日：2015-08-18
申请号：US14696785
申请日：2015-04-27
申请人： VIA TECHNOLOGIES, INC.
发明人： Ke-Yuan Chen , Jyh-Fong Lin
IPC分类号： H02H9/00 , H01L27/02
CPC分类号： H01L27/0262 , H01L27/0248 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.
摘要翻译：一种具有P型衬底的静电放电保护器件，在P型衬底中形成的公共N阱，形成在第一公共N阱中的公共N掺杂区域，其中公共N掺杂区域电连接到参考电压节点。该器件还具有形成在公共N阱中的公共P掺杂区域，其中公共P掺杂区域围绕公共N掺杂区域，公共P掺杂区域和公共N阱形成公共二极管，在P型衬底中形成的多个外围N阱并且围绕共用N阱，每个外围N阱包括P型掺杂区和N型掺杂区，其中P型掺杂区域电连接到多个I / O端子中的一个，以及形成在P型衬底中并设置在公共N阱和外围N阱之间的圆形P掺杂区域，并且环形P掺杂围绕普通N井的区域。

69. 发明申请

US20150227473A1 DATA STORAGE DEVICE AND DATA SCRAMBLING AND DESCRAMBLING METHOD 有权
标题翻译：数据存储设备和数据扫描和解密方法
公开(公告)号：US20150227473A1
公开(公告)日：2015-08-13
申请号：US14463991
申请日：2014-08-20
申请人： VIA TECHNOLOGIES, INC.
发明人： Lei FENG
IPC分类号： G06F12/14 , G06F21/60
CPC分类号： G06F21/602 , G06F21/79 , G06F21/85
摘要： A data scrambling and descrambling technology based on logical addresses. A data storage device with the data scrambling and descrambling technology includes a non-volatile memory and a controller. The controller generates a data scrambling seed according to a logical writing address issued from the host, scrambles the write data issued from the host with the data scrambling seed and then stores the scrambled write data into the non-volatile memory. The controller further generates a data descrambling seed according to a logical reading address issued from the host, and descrambles the read data retrieved from the non-volatile memory by the data descrambling seed. The controller further processes the descrambled read data for data checking and correction.
摘要翻译：基于逻辑地址的数据加扰和解扰技术。具有数据加扰和解扰技术的数据存储设备包括非易失性存储器和控制器。控制器根据从主机发出的逻辑写入地址生成数据加扰种子，用数据加扰种子对从主机发出的写入数据进行加扰，然后将加扰的写入数据存储到非易失性存储器中。控制器还根据从主机发出的逻辑读取地址产生数据解扰种子，并通过数据解扰种子解扰从非易失性存储器检索的读取数据。控制器进一步处理解扰的读取数据用于数据检查和校正。

70. 发明申请

US20150134978A1 SECURE BIOS TAMPER PROTECTION MECHANISM 有权
标题翻译：安全BIOS防篡改机制
公开(公告)号：US20150134978A1
公开(公告)日：2015-05-14
申请号：US14079299
申请日：2013-11-13
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry
IPC分类号： G06F21/57
CPC分类号： G06F21/572
摘要： An apparatus including a ROM, a selector, and a detector. The ROM has a partitions, each stored as plaintext, and a encrypted digests, each comprising an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more partitions responsive to an interrupt. The detector generates the interrupt at a combination of intervals and event occurrences, and accesses the one or more partitions and corresponding one or more encrypted digests upon assertion of the interrupt, and directs a microprocessor to generate corresponding one or more second digests corresponding to the one or more partitions and corresponding one or more decrypted digests corresponding to the one or more encrypted digests using the same algorithms and key that were employed to generate the first message digest and encrypted digests, and compares the one or more second digests with the one or more decrypted digests, and precludes the operation if the one or more second digests and the one or more decrypted digests are not pair wise equal.
摘要翻译：一种包括ROM，选择器和检测器的装置。 ROM具有每个存储为明文的分区和加密的摘要，每个分组包括与相应的一个分区相关联的第一摘要的加密版本。选择器响应于中断选择一个或多个分区。检测器以间隔和事件发生的组合生成中断，并且在断言中访问一个或多个分区和相应的一个或多个加密摘要，并指示微处理器产生对应于该中断的对应的一个或多个第二摘要或更多分区和对应于使用与生成第一消息摘要和加密摘要相同的算法和密钥的一个或多个加密摘要的对应的一个或多个解密摘要，并将该一个或多个第二摘要与一个或多个解密的摘要，并且如果一个或多个第二摘要和一个或多个解密的摘要不是成对相等的，则排除操作。

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