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1. 发明申请

US20190044537A1 Vertical Layered Finite Alphabet Iterative Decoding 审中-公开
公开(公告)号：US20190044537A1
公开(公告)日：2019-02-07
申请号：US16049724
申请日：2018-07-30
申请人： Codelucida, Inc.
发明人： Benedict J. Reynwar , David Declercq , Shiva Kumar Planjery
IPC分类号： H03M13/11
CPC分类号： H03M13/118 , H03M13/1108 , H03M13/1111 , H03M13/1117 , H03M13/114 , H03M13/116 , H03M13/6577
摘要： This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

2. 发明申请

US20190036548A1 PERMUTATION NETWORK DESIGNING METHOD, AND PERMUTATION CIRCUIT OF QC-LDPC DECODER 审中-公开
公开(公告)号：US20190036548A1
公开(公告)日：2019-01-31
申请号：US16145213
申请日：2018-09-28
申请人： Shenzhen EpoStar Electronics Limited CO.
发明人： Yu-Hua Hsiao , Heng-Lin Yen
IPC分类号： H03M13/11 , G06F9/30 , G06F11/10 , G11C16/08 , G06F12/126
CPC分类号： H03M13/1174 , G06F9/30018 , G06F9/30036 , G06F11/1012 , G06F12/126 , G11C16/08 , H03M13/1117 , H03M13/116 , H03M13/6502
摘要： A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit.

3. 发明申请

US20180269900A1 Decoding Method and Decoder for Low-Density Parity-Check Code 审中-公开
公开(公告)号：US20180269900A1
公开(公告)日：2018-09-20
申请号：US15982503
申请日：2018-05-17
申请人： Huawei Technologies Co., Ltd.
发明人： Jiaqi Fan , Xiaoshu Si
IPC分类号： H03M13/11
CPC分类号： H03M13/112 , H03M13/1117 , H03M13/1137 , H03M13/116 , H03M13/6508 , H04L1/00
摘要： A decoding method and a decoder for a low-density parity-check (LDPC) code, where the method includes dividing, by a decoder, an LDPC code C whose bit length is n into k LDPC codes D={D1,D2,K, Dk-1, Dk}, arranging, by the decoder, Di, i=1, 2, K, k−1, k by column to obtain transpose codes DT={D1T,D2T,K, Dk-1T, DkT} of the LDPC codes D, performing cyclic shift on DiT, i=1, 2, K, k−1, k by row according to values of corresponding elements in a target check matrix to obtain shift codes E={E1,E2,K,Et-1,Et}, where t is equal to a quantity of rows of the target check matrix, obtaining, by the decoder, t*m groups of LDPC subcodes F1, F2,K, Ftm-1, Ftm according to the shift codes E and a bit length d of the decoder, where Ej is divided into groups, Ej={(Ej)1d,(Ej)d+12d,K,(Ej)(m-2)d+1(m-1)d,(Ej)(m-1)d+1md}={F(j-1)m+1,F(j-1)m+1,K,Fjm-1,Fjm}, and m=┌l/d┐, and decoding, by the decoder, the m groups of LDPC subcodes to obtain a decoding result of the LDPC code C.

4. 发明申请

US20170359090A1 METHOD OF OPERATING DECODER FOR REDUCING COMPUTATIONAL COMPLEXITY AND METHOD OF OPERATING DATA STORAGE DEVICE INCLUDING THE DECODER 审中-公开
公开(公告)号：US20170359090A1
公开(公告)日：2017-12-14
申请号：US15613659
申请日：2017-06-05
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： DONG MIN SHIN , BEOM KYU SHIN , HEON HWA CHEONG , JUN JIN KONG , HONG RAK SON , YEONG GEOL SONG , SE JIN LIM
IPC分类号： H03M13/39 , H03M13/11
CPC分类号： H03M13/3927 , G06F11/10 , H03M13/1117
摘要： A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

5. 发明申请

US20170353194A1 LDPC Post-Processor Architecture and Method for Low Error Floor Conditions 审中-公开
公开(公告)号：US20170353194A1
公开(公告)日：2017-12-07
申请号：US15686361
申请日：2017-08-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Yaoyu Tao , Joyce Kwong
IPC分类号： H03M13/11
CPC分类号： H03M13/1117 , H03M13/1108 , H03M13/1111 , H03M13/1142 , H03M13/116
摘要： Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

6. 发明授权

US09692451B2 Non-binary low density parity check (NB-LDPC) codes for communication systems 有权
公开(公告)号：US09692451B2
公开(公告)日：2017-06-27
申请号：US14850539
申请日：2015-09-10
申请人： BROADCOM CORPORATION
发明人： Sudarsan Vasista Srinivasan Ranganathan , Ba-Zhong Shen
IPC分类号： H03M13/00 , H03M13/11 , H03M13/03
CPC分类号： H03M13/1171 , H03M13/036 , H03M13/1117 , H03M13/1168
摘要： A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. The device receives a non-binary low density parity check (NB-LDPC) coded signal. The device then decodes the NB-LDPC coded signal using a NB-LDPC matrix to generate estimates of information bits encoded therein. The NB-LDPC matrix is characterized by a base proto-matrix having elements that represent sub-matrices, and the elements are selected from a finite Galois field that includes symbols. In another example, the device encodes other information bits using a generator matrix to generate another NB-LDPC coded signal and then transmits this other NB-LDPC coded signal.

7. 发明申请

US20170149446A1 LDPC POST-PROCESSOR ARCHITECTURE AND METHOD FOR LOW ERROR FLOOR CONDITIONS 有权
公开(公告)号：US20170149446A1
公开(公告)日：2017-05-25
申请号：US14950659
申请日：2015-11-24
申请人： Texas Instruments Incorporated
发明人： Yaoyu Tao , Joyce Kwong
IPC分类号： H03M13/11
CPC分类号： H03M13/1117 , H03M13/1108 , H03M13/1111 , H03M13/1142 , H03M13/116
摘要： Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

8. 发明授权

US09432054B2 Method for decoding a correcting code with message passing, in particular for decoding LDPC codes or turbo codes 有权
标题翻译：用于对具有消息传递的校正码进行解码的方法，特别是用于解码LDPC码或turbo码
公开(公告)号：US09432054B2
公开(公告)日：2016-08-30
申请号：US14444027
申请日：2014-07-28
申请人： THALES
发明人： Benjamin Gadat , Nicholas Van Wambeke
IPC分类号： H03M13/00 , H03M13/11 , H03M13/29
CPC分类号： H03M13/1111 , H03M13/1117 , H03M13/2957
摘要： A method for iteratively decoding a word of a correcting code by an iterative decoding algorithm in the course of which, for each bit of said code word, at least one extrinsic information item is generated at each iteration, includes the following steps: an initial step of decoding by means of said iterative decoding algorithm; simultaneously, for each bit of said code word, a step of developing a criterion representing the number of oscillations of at least one extrinsic information item or of one extrinsic information item with regard to another extrinsic information item; if the decoding does not converge; a step of modifying the value of the bit of said code word for which said number of oscillations is highest; and, an additional step of decoding said at least one modified code word by means of said iterative decoding algorithm.
摘要翻译：一种用于通过迭代解码算法对纠错码的单词进行迭代解码的方法，其中对于所述码字的每个位，在每次迭代中生成至少一个外在信息项包括以下步骤：初始步骤通过所述迭代解码算法进行解码; 同时对于所述码字的每一位，相对于另一个外在信息项开发表示至少一个外在信息项或一个外在信息项的振荡次数的准则的步骤; 如果解码不收敛; 修改所述数量的振荡最高的所述码字的位的值的步骤; 以及通过所述迭代解码算法解码所述至少一个修改的代码字的附加步骤。

9. 发明授权

US09362951B2 Decoding method, decoding circuit, memory storage device and controlling circuit unit 有权
标题翻译：解码方法，解码电路，存储器和控制电路单元
公开(公告)号：US09362951B2
公开(公告)日：2016-06-07
申请号：US14145989
申请日：2014-01-01
申请人： PHISON ELECTRONICS CORP.
发明人： Chien-Fu Tseng
IPC分类号： G11C29/00 , H03M13/11 , G06F11/10
CPC分类号： H03M13/1105 , G06F11/1012 , H03M13/1108 , H03M13/1111 , H03M13/1117
摘要： A decoding method, a memory storage device, a memory controlling circuit unit and a decoding circuit for low density parity code (LDPC) are provided. The decoding method includes: reading a data bit of each memory cell; performing a parity check procedure on the data bits to generate a plurality of checks; in an iterative decoding of LDPC, obtaining a reliability message of each data bit according to the checks and deciding an index of an error bit from the data bits according to the reliability messages; determining whether the index of the error bit and the checks comply with a parity criteria; and if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding and outputting the index of the error bit. Accordingly, a decoding latency is decreased.
摘要翻译：提供了解码方法，存储器存储装置，存储器控制电路单元和用于低密度奇偶校验码（LDPC）的解码电路。解码方法包括：读取每个存储单元的数据位; 对数据位执行奇偶校验程序以产生多个检查; 在LDPC的迭代解码中，根据可靠性消息，根据检查并根据数据比特确定错误比特的索引，获得每个数据比特的可靠性消息; 确定错误位的索引和检查是否符合奇偶校验标准; 并且如果错误位的索引和检查符合奇偶校验标准，则停止迭代解码并输出错误位的索引。因此，解码等待时间减少。

10. 发明申请

US20160087648A1 Puncture-aware low density parity check (LDPC) decoding 有权
标题翻译：穿刺感低密度奇偶校验（LDPC）解码
公开(公告)号：US20160087648A1
公开(公告)日：2016-03-24
申请号：US14501719
申请日：2014-09-30
申请人： BROADCOM CORPORATION
发明人： Matthias Korb , Andrew John Blanksby
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/1105 , H03M13/005 , H03M13/1111 , H03M13/1117 , H03M13/116 , H03M13/1165 , H03M13/1174 , H03M13/118 , H03M13/1185 , H03M13/1188 , H03M13/255 , H03M13/2927 , H03M13/616 , H03M13/618 , H03M13/6362 , H03M13/6393
摘要： A communication device or device includes a processor that generates and interprets signals that are transmitted and received via a communication interface. The processor receives an LDPC coded signal, via the communication interface, that is generated by puncturing at least one parity bit from another LDPC coded signal that is generated based on an LDPC code characterized by a first LDPC matrix. The processor operates on the first LDPC matrix to generate a second LDPC matrix by excluding at least one column and at least one row from the first LDPC matrix. The number of columns and rows excluded from the first LDPC matrix is based on the number of bits punctured from the other LDPC coded signal to generate the LDPC coded signal. The processor then decodes the LDPC coded signal using the second LDPC matrix to make estimates of information bits encoded within the LDPC coded signal.
摘要翻译：通信设备或设备包括生成和解释通过通信接口发送和接收的信号的处理器。处理器经由通信接口接收通过从基于由第一LDPC矩阵表征的LDPC码生成的另一个LDPC编码信号中的至少一个奇偶校验位进行删截而产生的LDPC编码信号。处理器在第一LDPC矩阵上操作以通过从第一LDPC矩阵排除至少一列和至少一行来生成第二LDPC矩阵。从第一LDPC矩阵排除的列和行的数量是基于从其他LDPC编码信号中删除的比特数来生成LDPC编码信号的。然后，处理器使用第二LDPC矩阵对LDPC编码信号进行解码，以对在LDPC编码信号内编码的信息比特进行估计。

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