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61. 发明授权

US07495517B1 Techniques for dynamically adjusting the frequency range of phase-locked loops 有权
标题翻译：用于动态调整锁相环频率范围的技术
公开(公告)号：US07495517B1
公开(公告)日：2009-02-24
申请号：US11610892
申请日：2006-12-14
申请人： Tim Tri Hoang , Sergey Shumarayev
发明人： Tim Tri Hoang , Sergey Shumarayev
IPC分类号： H03L7/06 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/18
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/093 , H03L7/095 , H03L7/099 , Y10S331/02
摘要： Techniques are provided for dynamically adjusting the frequency range of phase-locked loops (PLLs). Phase detection circuitry in a PLL generates a control signal in response to a periodic input signal and a feedback signal. When the control signal deviates outside a valid range, the input frequency range of the PLL is dynamically adjusted to include the periodic input signal frequency. The input frequency range of the PLL is adjusted by changing one or more frequency ratios in the PLL. The resistance and/or capacitance of a loop filter in the PLL can be dynamically adjusted to control the bandwidth of the PLL.
摘要翻译：提供了用于动态调整锁相环（PLL）频率范围的技术。 PLL中的相位检测电路响应于周期性输入信号和反馈信号产生控制信号。当控制信号偏离有效范围时，PLL的输入频率范围被动态地调整为包括周期性输入信号频率。通过改变PLL中的一个或多个频率比来调整PLL的输入频率范围。可以动态地调整PLL中的环路滤波器的电阻和/或电容，以控制PLL的带宽。

62. 发明授权

US08626474B2 Simulation tool for high-speed communications links 有权
标题翻译：用于高速通信链接的仿真工具
公开(公告)号：US08626474B2
公开(公告)日：2014-01-07
申请号：US12762848
申请日：2010-04-19
申请人： Peng Li , Masashi Shimanouchi , Thungoc M. Tran , Sergey Shumarayev
发明人： Peng Li , Masashi Shimanouchi , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： G06F7/60 , G06G7/62 , G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/10
摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.
摘要翻译：提供了一种用于模拟高速通信链路系统的链路仿真工具。通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。链接仿真工具可以使用行为模型对每个子系统进行建模。行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎的链接系统。链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

63. 发明授权

US07855576B1 Versatile common-mode driver methods and apparatus 有权
标题翻译：多用途共模驱动方法和装置
公开(公告)号：US07855576B1
公开(公告)日：2010-12-21
申请号：US11407444
申请日：2006-04-19
申请人： Mei Luo , Sergey Shumarayev , Thungoc M. Tran , Simardeep Maangat
发明人： Mei Luo , Sergey Shumarayev , Thungoc M. Tran , Simardeep Maangat
IPC分类号： H03K19/0175 , H03K19/003
CPC分类号： H03K19/017509 , H04L25/0276
摘要： Methods and apparatus are provided for selectively setting a CM voltage for a transceiver, reducing the effect of current mismatch, and generating a voltage step that can be used for receiver detection. A circuit of the invention can include voltage generator circuitry operable to generate a plurality of voltage signals of substantially different voltages. The circuit can also include multiplexer circuitry with voltage inputs coupled to the voltage signals. The multiplexer circuitry can be operable to select a reference signal from among the voltage inputs. In addition, the circuit can include operational amplifier (“op-amp”) circuitry with a first input coupled to the reference signal and a second input coupled to an output signal of the op-amp circuitry.
摘要翻译：提供了用于选择性地设置收发器的CM电压的方法和装置，减少电流失配的影响，以及产生可用于接收机检测的电压步骤。本发明的电路可以包括可操作以产生具有实质上不同电压的多个电压信号的电压发生器电路。电路还可以包括具有耦合到电压信号的电压输入的多路复用器电路。多路复用器电路可以用于从电压输入中选择参考信号。此外，电路可以包括运算放大器（“运算放大器”）电路，其中耦合到参考信号的第一输入和耦合到运放电路的输出信号的第二输入。

64. 发明授权

US07460040B1 High-speed serial interface architecture for a programmable logic device 有权
标题翻译：用于可编程逻辑器件的高速串行接口架构
公开(公告)号：US07460040B1
公开(公告)日：2008-12-02
申请号：US11754670
申请日：2007-05-29
申请人： Thungoc M. Tran , Yu Xu , Kwong-Wen Wei , Sergey Shumarayev
发明人： Thungoc M. Tran , Yu Xu , Kwong-Wen Wei , Sergey Shumarayev
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H03K19/1774 , H03K19/17744
摘要： A high-speed serial interface for a programmable logic device includes a plurality of features to handle the various issues that may arise with data rates over 1 Gbps and particularly over 1.25 Gbps. Those features may include dynamic phase alignment to control clock-data skew, data realignment (e.g., bit slip circuitry) to account for channel-to-channel skew, full-duplex serializer and deserializer, out-of-range frequency support for low frequencies, and a soft-CDR mode.
摘要翻译：用于可编程逻辑器件的高速串行接口包括多个特征，以处理在1Gbps，特别是超过1.25Gbps的数据速率下可能出现的各种问题。这些特征可以包括动态相位对准以控制时钟数据偏移，数据重新对准（例如位移电路）以解决通道间通道偏移，全双工串行器和解串器，超低频率频率支持，和软CDR模式。

65. 发明申请

US20110257953A1 SIMULATION TOOL FOR HIGH-SPEED COMMUNICATIONS LINKS 有权
标题翻译：高速通信链接的仿真工具
公开(公告)号：US20110257953A1
公开(公告)日：2011-10-20
申请号：US12762848
申请日：2010-04-19
申请人： Peng Li , Masashi Shimanouchi , Thungoc M. Tran , Sergey Shumarayev
发明人： Peng Li , Masashi Shimanouchi , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/10
摘要： A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.
摘要翻译：提供了一种用于模拟高速通信链路系统的链路仿真工具。通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。链接仿真工具可以使用行为模型对每个子系统进行建模。行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎的链接系统。链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

66. 发明授权

US08705602B1 Equalizer circuitry with selectable tap positions and coefficients 有权
标题翻译：均衡器电路，具有可选择的抽头位置和系数
公开(公告)号：US08705602B1
公开(公告)日：2014-04-22
申请号：US12580587
申请日：2009-10-16
申请人： Weiqi Ding , Mengchi Liu , Mingde Pan , Thungoc M. Tran , Sergey Shumarayev
发明人： Weiqi Ding , Mengchi Liu , Mingde Pan , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03038 , H04L25/03343
摘要： Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).
摘要翻译：例如，用于串行数字数据信号的发射机均衡器电路包括用于输出通过延迟线电路传播的信号的多个不同延迟版本的抽头延迟线电路。均衡器电路还包括多个电流数模转换器（“DAC”）。均衡器电路还包括可控（例如，可编程）路由电路，用于可选地将信号的延迟版本路由到各种DAC。各种DAC所使用的电流强度也优选是可控的（例如，可编程的）。

67. 发明授权

US08417752B1 Offset cancellation in equalizer circuitry 有权
标题翻译：均衡器电路中的偏移消除
公开(公告)号：US08417752B1
公开(公告)日：2013-04-09
申请号：US12470254
申请日：2009-05-21
申请人： Doris Po Ching Chan , Simardeep Maangat , Thungoc M. Tran , Sergey Shumarayev
发明人： Doris Po Ching Chan , Simardeep Maangat , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： G06F7/10 , G06F7/00
CPC分类号： H04B3/04
摘要： An equalizer circuitry that includes an equalizer stage having a programmable current source is described. In one implementation, the programmable current source cancels voltage offset. Also, in one implementation, the programmable current source is programmable in user mode. Furthermore, in one implementation, the equalizer circuitry includes a plurality of equalizer stages including the equalizer stage having a programmable current source, where the equalizer stage having a programmable current source is a second equalizer stage in the plurality of equalizer stages. Also, in one implementation, the programmable current source includes a plurality of current sources coupled in parallel and a plurality of sets of control switches for controlling the plurality of current sources. Further, in one implementation, each current source of the plurality of current sources includes a transistor and each set of control switches of the plurality of sets of control switches is for controlling a respective current source and includes a pair of transistors for controlling the respective current source.
摘要翻译：描述了包括具有可编程电流源的均衡器级的均衡器电路。在一个实现中，可编程电流源消除电压偏移。而且，在一个实现中，可编程电流源可在用户模式下编程。此外，在一个实现中，均衡器电路包括多个均衡器级，包括具有可编程电流源的均衡器级，其中具有可编程电流源的均衡器级是多个均衡器级中的第二均衡器级。而且，在一个实现中，可编程电流源包括并联耦合的多个电流源和用于控制多个电流源的多组控制开关。此外，在一个实现中，多个电流源的每个电流源包括晶体管，并且多组控制开关中的每组控制开关用于控制相应的电流源，并且包括用于控制相应电流的一对晶体管资源。

68. 发明授权

US07863941B1 Techniques for canceling offsets in differential circuits 有权
标题翻译：差分电路消除偏移的技术
公开(公告)号：US07863941B1
公开(公告)日：2011-01-04
申请号：US12365585
申请日：2009-02-04
申请人： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev
发明人： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： H03K5/22
CPC分类号： H03K3/356139 , G11C7/065
摘要： A circuit includes a differential circuit that generates a differential output signal at first and second output nodes. The circuit also includes a first variable capacitor coupled to the first output node of the differential circuit, and a second variable capacitor coupled to the second output node of the differential circuit. A control circuit controls capacitances of the first and the second variable capacitors in response to a measurement of the differential output signal.
摘要翻译：电路包括在第一和第二输出节点处产生差分输出信号的差分电路。电路还包括耦合到差分电路的第一输出节点的第一可变电容器和耦合到差分电路的第二输出节点的第二可变电容器。响应于差分输出信号的测量，控制电路控制第一和第二可变电容器的电容。

69. 发明授权

US07245240B1 Integrated circuit serializers with two-phase global master clocks 有权
标题翻译：具有两相全球主时钟的集成电路串行器
公开(公告)号：US07245240B1
公开(公告)日：2007-07-17
申请号：US11370727
申请日：2006-03-07
申请人： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev
发明人： Toan Thanh Nguyen , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H03K5/15013
摘要： Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.
摘要翻译：提供集成电路串行化器电路，其将并行数据转换为集成电路上的串行数据。两相全局串行器主时钟发生器使用四相内部时钟来生成两相全局串行器主时钟。两相全局串行器主时钟使用分布路径全局分布在集成电路上。集成电路具有多个串行通信通道，每个通道具有相关联的串行器。每个串行器包含从全局串行器主时钟的两个相位导出多个时钟信号的电路。每个串行器使用派生时钟将并行数据转换为串行数据，以便通过其相关联的串行通信通道进行传输。串行器每个都包含两个较小的串行器，它们将第一和第二组并行数据转换为第一和第二串行输出。每个串行器中的2：1串行器合并第一个和第二个串行输出。

70. 发明授权

US07733982B2 Signal adjustment receiver circuitry 失效
标题翻译：信号调节接收器电路
公开(公告)号：US07733982B2
公开(公告)日：2010-06-08
申请号：US12511022
申请日：2009-07-28
申请人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
发明人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。

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