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61. 发明授权

US07590207B1 Modular serial interface in programmable logic device 有权
标题翻译：可编程逻辑器件中的模块化串行接口
公开(公告)号：US07590207B1
公开(公告)日：2009-09-15
申请号：US11256346
申请日：2005-10-20
申请人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
发明人： Sergey Y Shumarayev , Rakesh H Patel , Wilson Wong , Tim Tri Hoang , William Bereza
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H04J3/0688 , H04L7/033
摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.
摘要翻译：用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环）。这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

62. 发明授权

US08416845B1 Decision feedback equalization for variable input amplitude 有权
标题翻译：用于可变输入幅度的判决反馈均衡
公开(公告)号：US08416845B1
公开(公告)日：2013-04-09
申请号：US11484285
申请日：2006-07-11
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H03K5/1532
摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.
摘要翻译：提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。抽头系数可以由均衡电路自动调整。

63. 发明授权

US07639993B1 Power supply circuitry for data signal transceivers on integrated circuits 有权
标题翻译：集成电路上数据信号收发器的电源电路
公开(公告)号：US07639993B1
公开(公告)日：2009-12-29
申请号：US11295391
申请日：2005-12-05
申请人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
发明人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
IPC分类号： H04B1/04
CPC分类号： H04L7/033
摘要： The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.
摘要翻译：集成电路中的收发器电路的各种组件以各种方式放在一起，以便被提供电力以帮助防止组之间的噪声传播。在多通道收发器电路的情况下，可以在多个通道中的类似组之间存在各种数量的电源共享。

64. 发明授权

US07304507B1 Modular buffering circuitry for multi-channel transceiver clock and other signals 有权
标题翻译：用于多通道收发器时钟和其他信号的模块化缓冲电路
公开(公告)号：US07304507B1
公开(公告)日：2007-12-04
申请号：US11288496
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang
IPC分类号： H03K19/00
CPC分类号： H03K19/17736 , H03K19/17744
摘要： Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.
摘要翻译：在集成电路（例如现场可编程门阵列（“FPGA”）上的收发器电路块之间分配诸如参考时钟信号的信号的电路采用双向缓冲器而不是单向缓冲器。这允许所有缓冲器具有相同的结构，而不管物理位置如何，这有助于使用相同或基本相同的模块构建电路。相同的方法可以用于在收发器块之间分配其他类型的信号。例如，该方法可用于分配校准控制信号。

65. 发明授权

US07276937B2 Modular interconnect circuitry for multi-channel transceiver clock signals 有权
公开(公告)号：US07276937B2
公开(公告)日：2007-10-02
申请号：US11270718
申请日：2005-11-08
申请人： Tim Tri Hoang , Sergey Yuryevich Shumarayev
发明人： Tim Tri Hoang , Sergey Yuryevich Shumarayev
IPC分类号： H03K19/177
CPC分类号： G06F1/10 , H03K19/177 , H03K19/17736
摘要： Circuitry for distributing clock signals (e.g., reference clock signals) among a plurality of blocks of circuitry. Each block may include reference clock source circuitry and reference clock utilization circuitry. Each block also preferably includes an identical or substantially identical module of clock signal distribution circuitry that can (1) accept a signal from the source circuitry in that block, (2) apply any of several clock signals to the utilization circuitry in that block, and (3) connect to the similar module(s) of one or more adjacent blocks.

66. 发明授权

US08671305B1 Techniques for adjusting periodic signals based on data detection 有权
标题翻译：基于数据检测调整周期信号的技术
公开(公告)号：US08671305B1
公开(公告)日：2014-03-11
申请号：US13175604
申请日：2011-07-01
申请人： Shou-Po Shih , Tim Tri Hoang , Kazi Asaduzzaman
发明人： Shou-Po Shih , Tim Tri Hoang , Kazi Asaduzzaman
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： H04B10/6165 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/14 , H04L7/0004 , H04L7/0083 , H04L7/033
摘要： A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit is operable to generate a first phase detection signal based on a data signal and a first periodic signal. The phase frequency detector circuit is operable to generate a second phase detection signal based on second and third periodic signals. The data detection circuit is operable to generate a data detection signal based on the first phase detection signal. A multiplexer circuit is operable to provide one of the first and the second phase detection signals as a selected signal based on the data detection signal. The periodic signal generation circuit is operable to cause adjustments to phases of the first and the second periodic signals based on the selected signal.
摘要翻译：电路包括相位检测器电路，相位频率检测器电路，数据检测电路，多路复用器电路和时钟信号发生电路。相位检测器电路可操作以基于数据信号和第一周期信号产生第一相位检测信号。相位频率检测器电路可操作以基于第二和第三周期信号产生第二相位检测信号。数据检测电路可操作以基于第一相位检测信号产生数据检测信号。多路复用器电路可操作以基于数据检测信号提供第一和第二相位检测信号中的一个作为选择的信号。周期信号产生电路可操作以基于所选择的信号来调整第一和第二周期信号的相位。

67. 发明授权

US08559582B2 Techniques for varying a periodic signal based on changes in a data rate 有权
标题翻译：基于数据速率变化来改变周期性信号的技术
公开(公告)号：US08559582B2
公开(公告)日：2013-10-15
申请号：US12881160
申请日：2010-09-13
申请人： Tim Tri Hoang
发明人： Tim Tri Hoang
IPC分类号： H04L7/033
CPC分类号： H04L7/033 , H03L7/087 , H03L7/183
摘要： A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal. The phase adjustment circuit causes the phase of the second periodic signal and a phase of a third periodic signal to vary based on a variation in the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The circuit varies a frequency of the third periodic signal to correspond to changes in a data rate of the data signal between at least three different data rates that are based on at least three data transmission protocols.
摘要翻译：电路包括相位检测电路，相位调整电路和采样电路。相位检测电路将第一周期信号的相位与第二周期信号的相位进行比较，以产生控制信号。相位调整电路使得第二周期信号的相位和第三周期信号的相位根据控制信号的变化而变化。采样器电路对数据信号进行采样，以响应于第三周期信号产生采样数据信号。电路改变第三周期信号的频率，以对应于基于至少三个数据传输协议的至少三个不同数据速率之间的数据信号的数据速率的变化。

68. 发明授权

US08294500B1 Multi-phase interpolators and related methods 有权
标题翻译：多相内插器及相关方法
公开(公告)号：US08294500B1
公开(公告)日：2012-10-23
申请号：US12621493
申请日：2009-11-18
申请人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang , Van Ton-That
发明人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang , Van Ton-That
IPC分类号： H03H11/16
CPC分类号： G06G7/30
摘要： A phase interpolator circuit includes first and second transistors coupled to form a differential pair, a load circuit, a first set of switch circuits, a second set of switch circuits, and a current source. The first set of switch circuits are coupled between the first transistor and the load circuit. The second set of switch circuits are coupled between the second transistor and the load circuit. The current source provides current for the differential pair.
摘要翻译：相位插值器电路包括耦合以形成差分对的第一和第二晶体管，负载电路，第一组开关电路，第二组开关电路和电流源。第一组开关电路耦合在第一晶体管和负载电路之间。第二组开关电路耦合在第二晶体管和负载电路之间。电流源为差分对提供电流。

69. 发明授权

US07893726B1 Leakage compensation and improved setup/hold time in a dynamic flip-flop 有权
标题翻译：在动态触发器中泄漏补偿和改进的设置/保持时间
公开(公告)号：US07893726B1
公开(公告)日：2011-02-22
申请号：US11782443
申请日：2007-07-24
申请人： Vinh Van Ho , Tim Tri Hoang
发明人： Vinh Van Ho , Tim Tri Hoang
IPC分类号： G01R19/00
CPC分类号： G11C7/065 , G11C11/412 , H03K3/012 , H03K3/356139
摘要： A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.
摘要翻译：动态触发器包括形成适于接收差分数据的差分输入级的第一和第二输入级。触发器响应于复位信号被复位。为了确保正常操作，设置在第一和第二输入级之间的晶体管总是保持有效，以在接地端子和节点之间提供可以从电源电压充电的导电路径。为了改善触发器的设置和保持时间，时钟信号被施加到设置在第一输入级中的第一晶体管和设置在第二输入级中的第二晶体管。

70. 发明授权

US07994837B1 Techniques for phase interpolation 有权
标题翻译：相位插值技术
公开(公告)号：US07994837B1
公开(公告)日：2011-08-09
申请号：US12537634
申请日：2009-08-07
申请人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang
发明人： Vinh Van Ho , Tien Duc Pham , Tim Tri Hoang
IPC分类号： H03H11/16
CPC分类号： H03H11/22
摘要： A phase interpolator circuit can include first and second transistors coupled to form a differential pair, first and second load circuits, a first switch circuit coupled between the first transistor and the first load circuit, a second switch circuit coupled between the second transistor and the second load circuit, a current source circuit, and a third switch circuit coupled between the differential pair and the current source circuit. A phase interpolator circuit can include three differential pairs of transistors. Six periodic input signals having six different phases are concurrently provided to control inputs of transistors in the three differential pairs of transistors. The phase interpolator circuit generates a selected phase in an output signal in response to four of the periodic input signals.
摘要翻译：相位插值器电路可以包括耦合以形成差分对的第一和第二晶体管，第一和第二负载电路，耦合在第一晶体管和第一负载电路之间的第一开关电路，耦合在第二晶体管和第二负载电路之间的第二开关电路负载电路，电流源电路和耦合在差分对和电流源电路之间的第三开关电路。相位内插器电路可以包括三个差分对的晶体管。具有六个不同相位的六个周期性输入信号被同时提供以控制三个差分对晶体管中的晶体管的输入。相位插值器电路响应于四个周期性输入信号而在输出信号中产生所选择的相位。

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