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61. 发明授权

US07623407B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07623407B2
公开(公告)日：2009-11-24
申请号：US11839859
申请日：2007-08-16
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C16/26
摘要： A semiconductor device which continuously outputs data in synchronism with a first clock includes a clock generator which generates a second clock from the first clock which is externally supplied, a flip-flop circuit which operates in synchronism with the second clock, and receives the data, an output buffer circuit which outputs the output data from the flip-flop circuit outside, and a power supply circuit which includes a bandgap reference circuit, generates a voltage controlled by the bandgap reference circuit, and supplies the voltage as a power supply voltage to the clock generator, the flip-flop circuit, and the output buffer circuit.
摘要翻译：与第一时钟同步地连续地输出数据的半导体器件包括从外部提供的第一时钟产生第二时钟的时钟发生器，与第二时钟同步操作的触发器电路，并接收数据，输出缓冲电路，其输出来自外部的触发电路的输出数据和包括带隙基准电路的电源电路，产生由带隙基准电路控制的电压，并将电压作为电源电压供给到时钟发生器，触发器电路和输出缓冲电路。

62. 发明授权

US07414892B2 Nonvolatile semiconductor memory device which stores multivalue data 有权
标题翻译：存储多值数据的非易失性半导体存储器件
公开(公告)号：US07414892B2
公开(公告)日：2008-08-19
申请号：US11763690
申请日：2007-06-15
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
摘要翻译：参考电流产生电路产生至少一个参考电流。电压产生电路产生电压。感测放大器根据从电压产生电路提供的电压与从参考电流产生电路提供的参考电流将存储单元中的流量引起的电流进行比较。控制部分被提供有读出放大器的输出信号。当验证存储单元的阈值电压时，控制部分使得电压产生电路产生与从存储器单元读出数据时产生的读出电压相同的验证电压。

63. 发明授权

US07388788B2 Reference current generating circuit of nonvolatile semiconductor memory device 失效
公开(公告)号：US07388788B2
公开(公告)日：2008-06-17
申请号：US11401278
申请日：2006-04-11
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C11/34
CPC分类号： G11C7/14 , G11C11/5642 , G11C16/26 , G11C16/28 , G11C16/30
摘要： A reference current generating circuit has a plurality of current mirror circuits each having a mirror ratio different from another one, and generates a plurality of reference currents based on a current that flows to the reference memory cells. A plurality of sense amplifiers detects a current that flows to a selected memory cell based on the reference currents generated by the reference current generating circuit.

64. 发明授权

US07315475B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07315475B2
公开(公告)日：2008-01-01
申请号：US11496458
申请日：2006-08-01
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C11/5642
摘要： A sense amplifier has first and second input nodes. A reference memory cell is connected to the first input node. To the second input node, a constant current source circuit and a main memory cell are connected via a first transistor and a second transistor, respectively. A current mirror type load circuit is provided as a load circuit of the reference memory cell and the main memory cell. When a threshold voltage of the reference memory cell is adjusted, the first transistor is turned on and the second transistor is turned off. When the threshold voltage of the memory cell is adjusted at verification of writing to/erasing from the memory cell, the first transistor is turned off and the second transistor is turned on.
摘要翻译：读出放大器具有第一和第二输入节点。参考存储单元连接到第一输入节点。对于第二输入节点，恒流源电路和主存储单元分别经由第一晶体管和第二晶体管连接。提供电流镜式负载电路作为参考存储单元和主存储单元的负载电路。当调整参考存储单元的阈值电压时，第一晶体管导通，第二晶体管截止。当在从存储单元写入/擦除的验证中调整存储单元的阈值电压时，第一晶体管截止，第二晶体管导通。

65. 发明申请

US20060256616A1 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US20060256616A1
公开(公告)日：2006-11-16
申请号：US11453830
申请日：2006-06-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supple potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.
摘要翻译：半导体器件包括包括多个核的存储单元阵列，每个所述核包括一个块或多个块。所述半导体器件还包括第一电源线，所述第一电源线通常为所述多个芯提供，并提供数据读取电源电位; 第二电源线，其为所述多个核心共同提供，并且提供数据写入或擦除功率补偿电位; 以及电源线切换电路，其被设置用于所述多个芯中的每一个，并且根据所述多个核中的所述相应一个选择性地将所述多个核中的相应一个核连接到所述第一电源线或所述第二电源线多个核心处于数据读取模式或数据写入或擦除模式。

66. 发明申请

US20060227619A1 Nonvolatile semiconductor memory device which stores multivalue data 有权
标题翻译：存储多值数据的非易失性半导体存储器件
公开(公告)号：US20060227619A1
公开(公告)日：2006-10-12
申请号：US11401286
申请日：2006-04-11
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
摘要翻译：参考电流产生电路产生至少一个参考电流。电压产生电路产生电压。感测放大器根据从电压产生电路提供的电压与从参考电流产生电路提供的参考电流将存储单元中的流量引起的电流进行比较。控制部分被提供有读出放大器的输出信号。当验证存储单元的阈值电压时，控制部分使得电压产生电路产生与从存储器单元读出数据时产生的读出电压相同的验证电压。

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