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1. 发明申请

US20180158527A1 VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND RELATED CONTROLLERS 审中-公开
公开(公告)号：US20180158527A1
公开(公告)日：2018-06-07
申请号：US15883273
申请日：2018-01-30
申请人： Micron Technology, Inc.
发明人： Emanuele Confalonieri , Dionisio Minopoli
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C2207/104 , G11C2207/2209 , G11C2216/22
摘要： In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a NAND flash memory can be used in connection with read operations and a data register of the NAND flash memory can be used in connection with programming operations. Data registers of a plurality of non-volatile memory devices, such as NAND flash memory devices, can implement a distributed volatile cache (DVC) architecture in a managed memory device, according to some embodiments. According to certain embodiments, data can be moved and/or swapped between registers to perform certain operations in the non-volatile memory devices without losing the data stored while other operations are performed.

2. 发明授权

US09245590B2 Stacked die flash memory device with serial peripheral interface 有权
标题翻译：具有串行外设接口的堆叠式闪存设备
公开(公告)号：US09245590B2
公开(公告)日：2016-01-26
申请号：US14194248
申请日：2014-02-28
申请人： Winbond Electronics Corporation
发明人： Hui Chen , Teng Su
IPC分类号： G11C16/10 , G11C5/06
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , G11C16/08 , G11C16/107 , G11C16/16 , G11C16/20 , G11C16/32 , G11C2216/22 , G11C2216/24 , G11C2216/30 , H01L2224/32145 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
摘要翻译：任何数量的串行外围接口（“SPI”）闪存芯片可以使用任何所需的多芯片封装技术进行堆叠和封装，以实现各种功能的任何一种或组合，例如低每位成本，高密度存储，代码阴影到RAM，以及“执行就绪”应用程序的快速随机访问，同时保留SPI接口的优点。在器件制造期间，每个堆叠的管芯相对于封装中的另一个堆叠管芯被分配唯一的标识符或“管芯ID”。在正常操作期间，通过芯片选择指令使用独特的芯片ID，以使堆叠芯片之一能够响应SPI接口上的后续指令，同时禁用软件包中的其他堆叠芯片响应后续指令，但是对于某些“ 通用“指令，包括模切选择指令。支持堆叠模具的并行操作。

3. 发明申请

US20150248921A1 Stacked Die Flash Memory Device With Serial Peripheral Interface 有权
标题翻译：具有串行外设接口的堆叠模组闪存器件
公开(公告)号：US20150248921A1
公开(公告)日：2015-09-03
申请号：US14194248
申请日：2014-02-28
申请人： Winbond Electronics Corporation
发明人： Hui Chen , Teng Su
IPC分类号： G11C5/06 , G11C16/10
CPC分类号： G11C5/063 , G11C5/02 , G11C5/04 , G11C16/08 , G11C16/107 , G11C16/16 , G11C16/20 , G11C16/32 , G11C2216/22 , G11C2216/24 , G11C2216/30 , H01L2224/32145 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： Any number of Serial Peripheral Interface (“SPI”) flash memory die may be stacked and packaged using any desired multi-chip packaging technique to realize any one or combination of various capabilities such as low per-bit cost, high density storage, code shadowing to RAM, and fast random access for “execute in place” applications, while preserving the advantages of the SPI interface. During device manufacture, each of the stacked die is assigned a unique identifier or “Die ID” relative to the other stacked die in the package. During normal operations, the unique Die IDs are used by a Die Select instruction to enable one of the stacked die to respond to subsequent instructions on the SPI interface, while disabling the other stacked die in the package from responding to subsequent instructions but for certain “Universal” instructions which include the Die Select instruction. Concurrent operations by the stacked die are supported.
摘要翻译：任何数量的串行外围接口（“SPI”）闪存芯片可以使用任何所需的多芯片封装技术进行堆叠和封装，以实现各种功能的任何一种或组合，例如低每位成本，高密度存储，代码阴影到RAM，以及“执行就绪”应用程序的快速随机访问，同时保留SPI接口的优点。在器件制造期间，每个堆叠的管芯相对于封装中的另一个堆叠管芯被分配唯一的标识符或“管芯ID”。在正常操作期间，通过芯片选择指令使用独特的芯片ID，以使堆叠芯片之一能够响应SPI接口上的后续指令，同时禁用软件包中的其他堆叠芯片响应后续指令，但是对于某些“ 通用“指令，包括模切选择指令。支持堆叠模具的并行操作。

4. 发明授权

US08775719B2 NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
标题翻译：基于NAND的混合NVM设计，在单模并行接口中集成NAND和NOR
公开(公告)号：US08775719B2
公开(公告)日：2014-07-08
申请号：US12807996
申请日：2010-09-17
申请人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
发明人： Peter W. Lee , Fu-Chang Hsu , Kesheng Wang
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1075 , G11C2216/22
摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.
摘要翻译：非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。数据在同步时钟的上升沿和下降沿在并行接口上传输。并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由地址代码读取一个非易失性存储器阵列可能会中断读取另一个。一次读取操作具有两个子地址，一个命令之前传送一个。

5. 发明授权

US08700879B2 Concurrent memory operations 有权
标题翻译：并行记忆操作
公开(公告)号：US08700879B2
公开(公告)日：2014-04-15
申请号：US13223171
申请日：2011-08-31
申请人： Luca Porzio , Rodolphe Sequeira
发明人： Luca Porzio , Rodolphe Sequeira
IPC分类号： G06F12/00
CPC分类号： G06F12/08 , G06F12/0246 , G06F12/10 , G06F2212/2022 , G06F2212/657 , G06F2212/7201 , G11C7/22 , G11C2216/22
摘要： Subject matter disclosed herein relates to performing concurrent memory operations.
摘要翻译：本文公开的主题涉及执行并发存储器操作。

6. 发明申请

US20130100739A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130100739A1
公开(公告)日：2013-04-25
申请号：US13682023
申请日：2012-11-20
申请人： Renesas Electronics Corporation
发明人： Hiroaki TANIZAKI , Yuichi KUNORI , Tomoshi FUTATSUYA , Kenji KODA
IPC分类号： G11C16/34 , G11C16/16
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3454 , G11C16/3459 , G11C2216/22
摘要： The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.
摘要翻译：本发明提供一种具有能够缩短擦除时间并有效执行数据访问的非易失性存储功能的半导体器件。当在命令寄存器/控制电路的控制下，将擦除电压施加到布置在存储单元边界区域中的嵌入式擦除栅极布线，并且在浮动栅极和嵌入式擦除栅极之间传送电荷，从而执行擦除操作时，在施加擦除电压期间将读取选择电压施加到存储器栅极线和辅助栅极线，从而执行数据的读取。

7. 发明授权

US08325534B2 Concurrent operation of plural flash memories 有权
标题翻译：并行操作多个闪存
公开(公告)号：US08325534B2
公开(公告)日：2012-12-04
申请号：US12979425
申请日：2010-12-28
申请人： Tien-Chung Yang , Chia-Fu Lee , Yue-Der Chih
发明人： Tien-Chung Yang , Chia-Fu Lee , Yue-Der Chih
IPC分类号： G11C16/04
CPC分类号： G11C16/06 , G11C16/30 , G11C2216/22
摘要： A device includes an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
摘要翻译：设备包括地址存储设备。第一电路包括第一闪存，其被配置为顺序地接收第一和第二地址并将第一地址存储在地址存储设备中。第一电路具有第一组控制输入，用于使第一电路从与第一和第二地址中所选择的一个对应的第一闪存的单元上的读取，编程和擦除组合执行第一操作。第二电路包括被配置为接收第二地址的第二闪存。第二电路具有第二组控制输入，用于在执行第一操作时使第二电路从对应于第二地址的第二闪速存储器的单元读取数据。

8. 发明申请

US20120113721A1 FLEXIBLE MEMORY OPERATIONS IN NAND FLASH DEVICES 有权
标题翻译： NAND闪存器件中的灵活存储器操作
公开(公告)号：US20120113721A1
公开(公告)日：2012-05-10
申请号：US13348107
申请日：2012-01-11
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G06F12/0246 , G11C7/1045 , G11C8/08 , G11C8/10 , G11C16/0483 , G11C16/10 , G11C2216/22
摘要： A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing and activation of row circuits, column circuits, voltage generators, and local input/output path circuits for a corresponding memory access operation of the bank. Concurrent operations are executable in multiple banks to improve performance. Each bank has a page size that is configurable with page size configuration data such that only selected wordlines are activated in response to address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank.
摘要翻译：具有至少两个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小和核心控制器。核心控制器是每个银行本地的，并且管理银行的存储器访问操作，包括读取，编程和擦除操作。每个核心控制器控制行电路，列电路，电压发生器和本地输入/输出路径电路的定时和激活，用于存储体的相应存储器存取操作。并发操作可在多个银行中执行，以提高性能。每个银行的页面大小可配置页面大小的配置数据，以便仅响应于地址数据激活所选择的字线。在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。

9. 发明申请

US20120113715A1 Non-Volatile Memory With Improved Sensing By Reducing Source Line Current 有权
标题翻译：通过减少源极线电流改善感测的非易失性存储器
公开(公告)号：US20120113715A1
公开(公告)日：2012-05-10
申请号：US13285698
申请日：2011-10-31
申请人： Raul-Adrian Cernea
发明人： Raul-Adrian Cernea
IPC分类号： G11C16/26 , G11C16/04 , G11C16/06
CPC分类号： G11C7/062 , G11C7/04 , G11C7/067 , G11C7/08 , G11C7/22 , G11C7/227 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2211/5621 , G11C2216/14 , G11C2216/22
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。

10. 发明授权

US08125839B2 Memory device and method reducing fluctuation of read voltage generated during read while write operation 有权
标题翻译：存储器件和方法减少写操作期间读取期间产生的读取电压的波动
公开(公告)号：US08125839B2
公开(公告)日：2012-02-28
申请号：US12222635
申请日：2008-08-13
申请人： Jae-woo Im
发明人： Jae-woo Im
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C8/14 , G11C16/30 , G11C2216/22
摘要： According to example embodiments, a semiconductor memory device may include a write voltage generator configured to generate a write voltage to perform the write operation to at least one of a plurality of banks where the write voltage generator generates the write voltage to have a voltage level of a read voltage before the write operation changes to a read operation. The semiconductor device may also include a read voltage generator configured to generate a read voltage to perform the read operation to at least one of the other plurality of banks and/or a plurality of switches configured to switch a voltage applied to at least one of the banks to one of the write voltage and the read voltage in response to a plurality of control signals.
摘要翻译：根据示例实施例，半导体存储器件可以包括写入电压发生器，其被配置为产生写入电压，以对写入电压发生器产生写入电压的多个存储体中的至少一个进行写入操作，写入操作之前的读取电压变为读取操作。半导体器件还可以包括读取电压发生器，其被配置为产生读取电压以对其他多个存储体中的至少一个存储体执行读取操作，和/或多个开关被配置为切换施加到至少一个存储器响应于多个控制信号将其写入写入电压和读取电压之一。

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