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1. 发明授权

US07848160B2 Semiconductor storage device and method for operating the same 有权
标题翻译：半导体存储装置及其操作方法
公开(公告)号：US07848160B2
公开(公告)日：2010-12-07
申请号：US12333884
申请日：2008-12-12
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G11C7/22 , G11C16/06 , G11C7/02
CPC分类号： G11C7/18 , G11C7/12
摘要： A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.
摘要翻译：半导体存储装置包括连接到第一和第二列树的多个存储单元，以及从存储单元读取数据的感测电路。感测电路通过将连接到读选择的存储单元的列树电连接到感测节点并将连接到未选择的存储器单元的列树电连接到参考电路来执行读取操作传感线。

2. 发明授权

US07714637B2 Negative potential discharge circuit and method thereof 有权
标题翻译：负电位放电电路及其方法
公开(公告)号：US07714637B2
公开(公告)日：2010-05-11
申请号：US11812927
申请日：2007-06-22
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G05F3/02
CPC分类号： G11C5/147 , G11C5/145 , G11C16/30
摘要： A negative potential discharge circuit may include an internal voltage generating circuit and/or a discharge unit. The internal voltage generating circuit may be configured to generate a regulated output voltage based on a power supply voltage. The discharge unit may be configured to discharge a negative potential using the regulated output voltage. A method of discharging a negative potential may include generating a regulated output voltage based on a power supply voltage, and/or discharging a negative potential using the regulated output voltage.
摘要翻译：负电位放电电路可以包括内部电压产生电路和/或放电单元。内部电压发生电路可以被配置为基于电源电压产生稳定的输出电压。放电单元可以被配置为使用调节的输出电压来放电负电位。放电负电位的方法可以包括基于电源电压产生稳定的输出电压，和/或使用调节的输出电压来排出负电位。

3. 发明授权

US07605643B2 Voltage generation circuit and method thereof 有权
标题翻译：电压产生电路及其方法
公开(公告)号：US07605643B2
公开(公告)日：2009-10-20
申请号：US11812682
申请日：2007-06-21
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.
摘要翻译：电压产生电路可以包括静态电流电路和/或电流镜。静态电流电路可以包括第一电阻器。电流镜可以包括第二电阻器，第三电阻器和/或输出端子。

4. 发明授权

US07420863B2 Nonvolatile semiconductor memory device which stores multivalue data 失效
公开(公告)号：US07420863B2
公开(公告)日：2008-09-02
申请号：US11763743
申请日：2007-06-15
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

5. 发明授权

US07397716B2 Nonvolatile semiconductor memory device which stores multivalue data 有权
公开(公告)号：US07397716B2
公开(公告)日：2008-07-08
申请号：US11401286
申请日：2006-04-11
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

6. 发明申请

US20050117406A1 Semiconductor integrated circuit device with main cell array and fuse cell array 失效
标题翻译：具有主单元阵列和熔丝单元阵列的半导体集成电路器件
公开(公告)号：US20050117406A1
公开(公告)日：2005-06-02
申请号：US11033398
申请日：2005-01-12
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C5/00 , G11C5/14 , G11C16/04 , H01L29/78 , H03K5/153 , H03K5/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
摘要翻译：半导体集成电路器件包括主单元阵列，熔丝单元阵列，布置在主单元阵列处的主单元字线以及布置在熔丝单元阵列处的熔丝单元字线。熔丝单元字线形成在与主单元字线的方向相同的方向上。

7. 发明授权

US06829194B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US06829194B2
公开(公告)日：2004-12-07
申请号：US10307283
申请日：2002-12-02
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义用作数据擦除单位的存储单元范围。半导体设备具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作在第一存储器和第二存储体，同时在第一和第二存储体的另一个中进行数据写入或擦除操作。

8. 发明授权

US06711066B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06711066B2
公开(公告)日：2004-03-23
申请号：US10198170
申请日：2002-07-19
申请人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
发明人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
IPC分类号： G11C700
CPC分类号： G11C16/107 , G11C16/30 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C16/3477
摘要： A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
摘要翻译：电位产生电路产生两种类型的擦除验证阈值EVT1和EVT2。这些值满足EVT2 = EVT1 +（OEVT-EVTL）的关系。 OEVT是过擦除验证阈值。当擦除验证阈值设定为EVT2时，数据擦除后阈值电压分布的下限高于OEVT。 EVTL是数据擦除后的阈值电压分布的下限，擦除验证阈值设定为EVT1，低于OEVT。根据操作模式切换擦除验证阈值EVT1和EVT2。在写入/擦除测试期间，例如，擦除验证阈值被设置为EVT2。另一方面，在正常操作期间，将擦除验证阈值设置为EVT1。

9. 发明授权

US06512693B2 Semiconductor device that enables simultaneous read and write/erase operation 有权
标题翻译：实现同时读/写/擦除操作的半导体器件
公开(公告)号：US06512693B2
公开(公告)日：2003-01-28
申请号：US09987981
申请日：2001-11-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C1604
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

10. 发明授权

US06480427B2 Negative-potential detecting circuit having an enhanced sensitivity of detecting negative potentials 有权
公开(公告)号：US06480427B2
公开(公告)日：2002-11-12
申请号：US09789712
申请日：2001-02-22
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C16/06
摘要： A negative-potential detecting circuit includes first and second resistance elements connected in series between an output end of a constant-current source for outputting a constant current and a negative-potential node for generating a negative potential, a third resistance element connected between a connection node between the first and second resistance elements and a fixed-potential node, and a comparator for comparing a potential of a connection node between the constant-current source and the first resistance element and a reference potential with each other. The comparator detects a level of a negative potential by comparing the potential of the connection node and the reference potential.

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