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61. 发明授权

US07989915B2 Vertical electrical device 有权
标题翻译：垂直电气设备
公开(公告)号：US07989915B2
公开(公告)日：2011-08-02
申请号：US11485034
申请日：2006-07-11
申请人： Jeffrey F. DeNatale , Stefan C. Lauxtermann , Per-Olov Pettersson
发明人： Jeffrey F. DeNatale , Stefan C. Lauxtermann , Per-Olov Pettersson
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11 , H01L29/40
CPC分类号： H01L21/76898 , H01G4/005 , H01G4/06 , H01G4/40 , H01L21/486 , H01L23/49827 , H01L23/50 , H01L2223/6622 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A vertical electrical device includes a region in a substrate extending from a surface of the substrate, the region having an inner wall and an outer wall circumscribing the inner wall. An inner electrically conductive layer is disposed on the inner wall and an outer electrically conductive layer is disposed on the outer wall, with an electrically insulative material disposed between the inner and outer layers. An electrical conductor in the substrate is bounded by the inner electrically conductive layer.
摘要翻译：垂直电气装置包括从衬底的表面延伸的衬底中的区域，该区域具有内壁和限定内壁的外壁。内导电层设置在内壁上，外导电层设置在外壁上，电绝缘材料设置在内层和外层之间。衬底中的电导体由内部导电层限定。

62. 发明授权

US07985959B2 Self-aligned vertical bipolar junction transistor for phase change memories 有权
标题翻译：用于相变存储器的自对准垂直双极结型晶体管
公开(公告)号：US07985959B2
公开(公告)日：2011-07-26
申请号：US12218171
申请日：2008-07-11
申请人： Michele Magistretti , Fabio Pellizzer , Augusto Benvenuti , Marcello Mariani
发明人： Michele Magistretti , Fabio Pellizzer , Augusto Benvenuti , Marcello Mariani
IPC分类号： H01L29/02 , H01L27/082
CPC分类号： H01L27/1022 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A phase change memory may include self-aligned polysilicon vertical bipolar junction transistors used as select devices. The bipolar junction transistors may be formed with double shallow trench isolation. For example, the emitters of each bipolar transistor may be defined by a first set of parallel trenches in one direction and a second set of parallel trenches in the opposite direction. In some embodiments, the formation of parasitic PNP transistors between adjacent emitters may be avoided.
摘要翻译：相变存储器可以包括用作选择器件的自对准多晶硅垂直双极结型晶体管。双极结型晶体管可以形成双浅沟槽隔离。例如，每个双极晶体管的发射极可以由一个方向上的第一组平行沟槽和相反方向上的第二组平行沟槽限定。在一些实施例中，可以避免在相邻发射器之间形成寄生PNP晶体管。

63. 发明授权

US07932580B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07932580B2
公开(公告)日：2011-04-26
申请号：US11961516
申请日：2007-12-20
申请人： Mitsuru Soma , Hirotsugu Hata , Yoshimasa Amatatsu
发明人： Mitsuru Soma , Hirotsugu Hata , Yoshimasa Amatatsu
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7322 , H01L29/6625 , H01L29/66272 , H01L29/735
摘要： In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.
摘要翻译：在衬底和外延层中，形成隔离区以将衬底和外延层分成多个元件形成区域。每个隔离区域通过将第一和第二P型掩埋扩散层与P型扩散层连接而形成。通过在第一P型埋入扩散层和P型扩散层之间设置第二P型埋入扩散层，第一P型埋入扩散层的横向扩散宽度减小。该结构允许减小隔离区域的形成区域。

64. 发明授权

US07923783B2 Semiconductor memory device having resistance element with two conductors 有权
标题翻译：半导体存储器件具有具有两个导体的电阻元件
公开(公告)号：US07923783B2
公开(公告)日：2011-04-12
申请号：US12408287
申请日：2009-03-20
申请人： Takumi Abe
发明人： Takumi Abe
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L27/10 , H01L29/74 , H01L23/62 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/00 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11 , H01L23/48
CPC分类号： H01L27/105 , H01L27/11526 , H01L28/20 , Y10S257/904
摘要： A semiconductor memory device according to an embodiment of the present invention includes a resistance element which is constructed with a first conductor which extends in a first direction and is connected to a first contact; a second conductor which extends in said first direction and is connected to a second contact; and a first insulation film which exists between said first conductor and said second conductor, said first insulation film also having an opening in which a third conductor which connects said first conductor and said second conductor is arranged.
摘要翻译：根据本发明的实施例的半导体存储器件包括：电阻元件，其被构造为具有沿第一方向延伸并连接到第一触点的第一导体; 第二导体，其沿所述第一方向延伸并连接到第二触点; 以及存在于所述第一导体和所述第二导体之间的第一绝缘膜，所述第一绝缘膜还具有开口，在所述开口中布置有连接所述第一导体和所述第二导体的第三导体。

65. 发明申请

US20100301453A1 High-Voltage BJT Formed Using CMOS HV Processes 有权
标题翻译：使用CMOS HV工艺形成高压BJT
公开(公告)号：US20100301453A1
公开(公告)日：2010-12-02
申请号：US12750503
申请日：2010-03-30
申请人： Tao Wen Chung , Po-Yao Ke , Wei-Yang Lin , Shine Chung
发明人： Tao Wen Chung , Po-Yao Ke , Wei-Yang Lin , Shine Chung
IPC分类号： H01L27/082
CPC分类号： H01L27/0823 , H01L29/0692 , H01L29/0821 , H01L29/7322 , H01L29/735
摘要： An integrated circuit device includes a semiconductor substrate having a top surface; at least one insulation region extending from the top surface into the semiconductor substrate; a plurality of base contacts of a first conductivity type electrically interconnected to each other; and a plurality of emitters and a plurality of collectors of a second conductivity type opposite the first conductivity type. Each of the plurality of emitters, the plurality of collectors, and the plurality of base contacts is laterally spaced apart from each other by the at least one insulation region. The integrated circuit device further includes a buried layer of the second conductivity type in the semiconductor substrate, wherein the buried layer has an upper surface adjoining bottom surfaces of the plurality of collectors.
摘要翻译：集成电路器件包括具有顶表面的半导体衬底; 至少一个绝缘区域，从所述顶表面延伸到所述半导体衬底中; 多个彼此电互连的第一导电类型的基座触头; 以及与第一导电类型相反的第二导电类型的多个发射极和多个集电极。多个发射器，多个集光器和多个基座触点中的每一个通过至少一个绝缘区域彼此横向间隔开。集成电路装置还包括在半导体衬底中的第二导电类型的掩埋层，其中掩埋层具有邻接多个集电极的底表面的上表面。

66. 发明授权

US07800143B2 Dynamic random access memory with an amplified capacitor 有权
标题翻译：具有放大电容器的动态随机存取存储器
公开(公告)号：US07800143B2
公开(公告)日：2010-09-21
申请号：US11615982
申请日：2006-12-24
申请人： Hyun-Jin Cho
发明人： Hyun-Jin Cho
IPC分类号： H01L29/76 , H01L29/94 , H01L21/331 , H01L21/8222 , H01L27/082
CPC分类号： H01L27/1021 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/1203
摘要： A memory cell and methods of making and operating the same are provided. In one aspect, a method of forming a memory cell is provided that includes forming a MOS transistor that has a gate, a source region and a drain region. A bipolar transistor is formed that has a collector, a base and an emitter. The emitter of the bipolar transistor is formed to serve as the source region for the MOS transistor and the base of the bipolar transistor is formed to serve as a capacitive charge storage region for the memory cell.
摘要翻译：提供了一种存储单元及其制作和操作方法。一方面，提供一种形成存储单元的方法，包括形成具有栅极，源极区和漏极区的MOS晶体管。形成具有集电极，基极和发射极的双极晶体管。双极晶体管的发射极被形成为用于MOS晶体管的源极区域，并且双极晶体管的基极形成为用作存储器单元的电容电荷存储区域。

67. 发明授权

US07795703B1 Selective and non-selective epitaxy for base intergration in a BiCMOS process 有权
标题翻译：选择性和非选择性外延，用于BiCMOS工艺中的基础整合
公开(公告)号：US07795703B1
公开(公告)日：2010-09-14
申请号：US12290987
申请日：2008-11-05
申请人： Greg D. U'Ren
发明人： Greg D. U'Ren
IPC分类号： H01L27/082
CPC分类号： H01L29/732 , H01L21/8249 , H01L29/1004 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer extends over the first and second isolation regions. The bipolar transistor further includes a base layer situated on the epitaxial extension layer, where the base layer includes an epitaxial base, and where the epitaxial base includes a usable emitter formation area. The active area has a first width and the usable emitter formation area has a second width, where the second width is at least as large as the first width.
摘要翻译：根据一个示例性实施例，双极晶体管包括位于衬底中的第一和第二隔离区之间的有源区。双极晶体管还包括位于有源区上的外延延伸层，其中外延延伸层在第一和第二隔离区上延伸。双极晶体管还包括位于外延延伸层上的基极层，其中基极层包括外延基极，并且其中外延基底包括可用的发射极形成区域。有源区域具有第一宽度，并且可用的发射体形成区域具有第二宽度，其中第二宽度至少与第一宽度一样大。

68. 发明申请

US20100213575A1 Profile Design for Lateral-Vertical Bipolar Junction Transistor 有权
标题翻译：侧向双极结晶体管剖面设计
公开(公告)号：US20100213575A1
公开(公告)日：2010-08-26
申请号：US12715103
申请日：2010-03-01
申请人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
发明人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
IPC分类号： H01L27/082
CPC分类号： H01L29/0692 , H01L21/8224 , H01L27/0203 , H01L27/0821 , H01L29/735
摘要： A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.
摘要翻译：横向垂直双极结型晶体管（LVBJT）包括在衬底上的第一导电类型的阱区; 在该区域上的第一电介质; 以及在第一电介质上的第一电极。与第一导电类型相反的第二导电类型的集电器位于第一电极的阱区域和第一侧上，并且与第一电极相邻。第二导电类型的发射极位于第一电极的阱区和第二侧，并且与第一电极相邻，其中第二侧与第一侧相对。具有比集电体低的杂质浓度的集电极延伸区域与集电极邻接并面向发射极。 LVBJT没有面向集电极的任何发射极延伸区域并且与发射极相邻。

69. 发明申请

US20100181649A1 POLYSILICON PILLAR BIPOLAR TRANSISTOR WITH SELF-ALIGNED MEMORY ELEMENT 有权
标题翻译：具有自对准记忆元件的多晶硅柱状双极晶体管
公开(公告)号：US20100181649A1
公开(公告)日：2010-07-22
申请号：US12357912
申请日：2009-01-22
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1683
摘要： Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
摘要翻译：本文描述了具有与双极结晶体管存取装置的发射极自对准的存储元件的存储单元以及用于制造这种装置的方法。如本文所述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括双极结型晶体管，其包括由掺杂多晶硅柱构成的发射极。存储单元包括在发射器上的绝缘元件，并且具有延伸穿过绝缘层的开口，开口以发射器为中心。存储单元还包括在开口内的存储元件并电耦合到发射器。

70. 发明授权

US07732896B2 Semiconductor apparatus and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07732896B2
公开(公告)日：2010-06-08
申请号：US11480428
申请日：2006-07-05
申请人： Kouzi Hayasi
发明人： Kouzi Hayasi
IPC分类号： H01L27/082
CPC分类号： H01L29/7304
摘要： A semiconductor apparatus comprises a plurality of transistor devices including a control terminal being inputted with a control signal and a first and a second terminals that a current flows therein according to the control signal, and a plurality of substrate conductive portions each formed in a region different from a region where the plurality of transistor devices are formed therein, wherein the transistor devices are connected to the substrate conductive portions, and each of the substrate conductive portion includes a semiconductor layer separated from other substrate conductive portions.
摘要翻译：一种半导体装置，包括多个晶体管器件，包括输入控制信号的控制端子和电流根据控制信号流入其中的第一和第二端子，以及多个衬底导电部件，每个衬底导电部件形成在不同的区域中从其中形成有多个晶体管器件的区域，其中晶体管器件连接到衬底导电部分，并且每个衬底导电部分包括与其它衬底导电部分分离的半导体层。

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