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1. 发明授权

US08832010B2 Electronic synapses from stochastic binary memory devices 有权
标题翻译：随机二进制存储器件的电子突触
公开(公告)号：US08832010B2
公开(公告)日：2014-09-09
申请号：US13343371
申请日：2012-01-04
申请人： Bipin Rajendran , Mark B. Ritter
发明人： Bipin Rajendran , Mark B. Ritter
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049
摘要： According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.
摘要翻译：根据技术，电子设备被配置为对应于生物突触的特征。电子装置包括平行布置的多个双极性电阻器以形成电子突触，连接到电子突触的一端和第一电子神经元的轴突连接，以及连接到电子突触的另一端的树突状连接和第二电子神经元。电子突触中突触传导的增加和减少是基于在低电阻状态和高电阻状态之间切换多个双极性电阻器的概率。

2. 发明授权

US08824218B2 Compact low-power asynchronous resistor-based memory read operation and circuit 有权
标题翻译：紧凑型低功耗基于异步电阻的存储器读操作和电路
公开(公告)号：US08824218B2
公开(公告)日：2014-09-02
申请号：US13552932
申请日：2012-07-19
申请人： Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

3. 发明授权

US08559217B2 Phase change material cell with stress inducer liner 有权
标题翻译：相变材料电池与应力诱导衬管
公开(公告)号：US08559217B2
公开(公告)日：2013-10-15
申请号：US12964980
申请日：2010-12-10
申请人： Catherine A. Dubourdieu , Martin M. Frank , Bipin Rajendran , Alejandro G. Schrott
发明人： Catherine A. Dubourdieu , Martin M. Frank , Bipin Rajendran , Alejandro G. Schrott
IPC分类号： G11C11/00
CPC分类号： H01L45/1608 , G11C11/22 , G11C13/0004 , G11C13/0069 , G11C2013/0095 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/143 , H01L45/144
摘要： An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.
摘要翻译：所公开的示例实施例是相变存储单元。存储单元包括相变材料和位于相变材料附近的换能器。相变材料可在至少非晶状态和结晶状态之间切换。换能器被配置为当相变材料从非晶状态转变为结晶状态时激活。在特定实施例中，换能器是铁电材料。

4. 发明授权

US08527438B2 Producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array 有权
标题翻译：在超密集突触交叉阵列中产生尖峰时序依赖性可塑性
公开(公告)号：US08527438B2
公开(公告)日：2013-09-03
申请号：US12645479
申请日：2009-12-22
申请人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
发明人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
IPC分类号： G06E1/00 , G06E3/00 , G06F15/18 , G06G7/00
CPC分类号： G06N3/049 , G06N3/0635
摘要： Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor.
摘要翻译：本发明的实施方案涉及在用于神经形态系统的超密集突触交叉阵列中产生尖峰时间依赖性可塑性。本发明的一个方面包括当电子神经元尖峰时，警报脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当尖峰电子神经元发出警报脉冲时，门脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当每个电子神经元接收到警报脉冲时，从接收警报脉冲的每个电子神经元发送响应脉冲到尖峰电子神经元。响应脉冲是从接收警报脉冲的电子神经元的最后一次尖峰起的时间的函数。此外，门脉冲和响应脉冲的组合能够增加或降低可变状态电阻器的电导。

5. 发明申请

US20120259804A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
公开(公告)号：US20120259804A1
公开(公告)日：2012-10-11
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

6. 发明申请

US20120120701A1 TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 审中-公开
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20120120701A1
公开(公告)日：2012-05-17
申请号：US13350823
申请日：2012-01-16
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

7. 发明授权

US07965537B2 Phase change memory with finite annular conductive path 有权
标题翻译：具有有限环形导电路径的相变存储器
公开(公告)号：US07965537B2
公开(公告)日：2011-06-21
申请号：US12491816
申请日：2009-06-25
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16 , Y10T29/49002
摘要： A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance.
摘要翻译：相变存储器件及其编程方法。该方法包括确定相变存储器件中的存储器单元的最大可能电阻。该方法包括确定相变存储器件中存储单元的高电阻状态。该方法包括接收将相变存储器件中的目标存储单元编程为高电阻状态的请求。该方法还包括将相变存储器件中的目标存储单元重置为高电阻状态，使得目标存储单元的高电阻状态的阻抗比最大可能的电阻小。在本发明的一个实施例中，相变存储器件中的存储单元的高电阻状态比最大可能电阻小至少10％。

8. 发明申请

US20110134676A1 RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE 有权
标题翻译：具有非和（非）结构的电阻式存储器件
公开(公告)号：US20110134676A1
公开(公告)日：2011-06-09
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C7/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

9. 发明申请

US20110119215A1 HARDWARE ANALOG-DIGITAL NEURAL NETWORKS 有权
标题翻译：硬件模拟数字神经网络
公开(公告)号：US20110119215A1
公开(公告)日：2011-05-19
申请号：US12618101
申请日：2009-11-13
申请人： Bruce G. Elmegreen , Ralph Linsker , Dennis M. Newns , Bipin Rajendran
发明人： Bruce G. Elmegreen , Ralph Linsker , Dennis M. Newns , Bipin Rajendran
IPC分类号： G06N3/06
CPC分类号： G06N3/0635 , G06N3/063
摘要： An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller.
摘要翻译：模拟数字交叉点网络包括多个行和列，多个突触节点，多个突触节点中的每个突触节点设置在多个行和列的行和列的交点处，其中每个突触所述多个突触节点的节点包括与其相关联的权重，与所述多个列中的每列相关联的列控制器，其中每个列控制器被设置为使能与所述列控制器通信的突触节点处的权重变化，以及与多个行的每一行相关联的行控制器，其中每个行控制器被设置为控制与所述行控制器通信的突触节点处的权重变化。

10. 发明申请

US20110116307A1 PHASE CHANGE MEMORY DEVICE SUITABLE FOR HIGH TEMPERATURE OPERATION 有权
标题翻译：相变式存储器件，适用于高温操作
公开(公告)号：US20110116307A1
公开(公告)日：2011-05-19
申请号：US12619362
申请日：2009-11-16
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
IPC分类号： H01L45/00 , G11C11/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.
摘要翻译：一种相变存储单元，包括底部电极，从底部电极分离的顶部电极和沉积在底部电极和顶部电极之间的生长主导的相变材料，并且与底部电极和顶部电极接触并被绝缘材料包围在其侧壁。处于复位状态的相变存储单元仅包括在相变存储单元的有效体积内的以生长为主的相变材料的非晶相。

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