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61. 发明授权

US08603876B2 Dynamic memory cell methods 有权
标题翻译：动态存储单元方法
公开(公告)号：US08603876B2
公开(公告)日：2013-12-10
申请号：US12542802
申请日：2009-08-18
申请人： Win K. Luk , Jin Cai
发明人： Win K. Luk , Jin Cai
IPC分类号： H01L21/8242
CPC分类号： G11C11/4097 , G11C7/18 , G11C8/16 , G11C11/405 , H01L21/28079 , H01L21/84 , H01L27/10873 , H01L29/495
摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
摘要翻译：公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

62. 发明申请

US20130320423A1 WRAP-AROUND FIN FOR CONTACTING A CAPACITOR STRAP OF A DRAM 有权
公开(公告)号：US20130320423A1
公开(公告)日：2013-12-05
申请号：US13484739
申请日：2012-05-31
申请人： Felix Beaudoin , Stephen M. Lucarini , Xinhui Wang , Xinlin Wang
发明人： Felix Beaudoin , Stephen M. Lucarini , Xinhui Wang , Xinlin Wang
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10867 , H01L27/10826 , H01L27/10829 , H01L27/10879 , H01L27/1207 , H01L27/1211
摘要： A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

63. 发明授权

US08569126B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08569126B2
公开(公告)日：2013-10-29
申请号：US13584253
申请日：2012-08-13
申请人： Yoshihiro Takao
发明人： Yoshihiro Takao
IPC分类号： H01L21/8238 , H01L21/8242
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207 , H01L27/11
摘要： A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.
摘要翻译：半导体器件包括其中限定了存储单元的有源区的硅衬底，形成在器件隔离绝缘膜上以在第一方向上延伸的栅电极，形成在硅衬底和栅电极上的第一绝缘膜，所述第一插塞形成为穿透所述第一绝缘膜，与所述栅极电极和所述第一有源区域重叠，并且在垂直于所述第一方向的第二方向上延伸，穿过所述第二有源区域上方的所述第一绝缘膜的第二插塞，形成在第一绝缘膜上的第二绝缘膜和埋在第二绝缘膜中的互连，并且形成为沿着第二方向从第一插塞的侧表面退回并且仅覆盖第一插头的上表面的一部分。

64. 发明授权

US08518773B2 Method of fabricating semiconductor capacitor 失效
标题翻译：制造半导体电容器的方法
公开(公告)号：US08518773B2
公开(公告)日：2013-08-27
申请号：US13616882
申请日：2012-09-14
申请人： David Vaclav Horak , Shom Ponoth , Hosadurga Shobha , Chih-Chao Yang
发明人： David Vaclav Horak , Shom Ponoth , Hosadurga Shobha , Chih-Chao Yang
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/88 , H01L21/3105 , H01L21/31111 , H01L21/3212
摘要： A method of fabricating a semiconductor capacitor includes forming a cavity in a first dielectric layer. Then, a nitride stack comprising a slow-etch nitride layer disposed between two fast-etch nitride layers is deposited in the cavity. Next, a portion of the nitride stack is etched within the cavity. Continuing, a metal plug is deposited in the cavity. The fast-etch nitride layers of the nitride stack are removed while preserving the slow-etch nitride layer of the nitride stack. A first metal layer is deposited over the slow-etch nitride layer, a second dielectric layer is deposited over the first metal layer, and a second metal layer is deposited over the second dielectric layer.
摘要翻译：制造半导体电容器的方法包括在第一电介质层中形成空腔。然后，将包括设置在两个快速蚀刻氮化物层之间的缓蚀刻氮化物层的氮化物堆叠沉积在空腔中。接下来，在空腔内蚀刻氮化物叠层的一部分。继续，金属塞被沉积在空腔中。去除氮化物叠层的快速蚀刻氮化物层，同时保留氮化物叠层的缓蚀刻氮化物层。在慢蚀刻氮化物层上沉积第一金属层，在第一金属层上沉积第二介电层，并且在第二介电层上沉积第二金属层。

65. 发明授权

US08501560B2 Method for manufacturing thin film capacitor and thin film capacitor obtained by the same 有权
标题翻译：制造薄膜电容器和薄膜电容器的方法
公开(公告)号：US08501560B2
公开(公告)日：2013-08-06
申请号：US13067800
申请日：2011-06-28
申请人： Hideaki Sakurai , Toshiaki Watanabe , Nobuyuki Soyama , Guillaume Guegan
发明人： Hideaki Sakurai , Toshiaki Watanabe , Nobuyuki Soyama , Guillaume Guegan
IPC分类号： H01L21/8242 , H01L21/00 , H01L21/20
CPC分类号： H01L28/60 , B82Y30/00 , C04B35/4682 , C04B2235/3213 , C04B2235/441 , C04B2235/781 , C04B2235/785 , C04B2235/787 , H01G4/01 , H01G4/1227 , H01G4/33 , H01L21/02197 , H01L21/02282 , H01L28/55 , H01L28/65
摘要： A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.
摘要翻译：薄膜电容器的特征在于形成下电极，将组合物涂覆在下电极上，而不施加温度大于300℃的退火工艺，在环境温度至500℃的范围内的预定温度下干燥并在500〜800℃的范围内的预定温度下煅烧并高于干燥温度。从涂覆到煅烧的过程进行从涂覆到煅烧一次或至少两次的过程，或者从涂覆到干燥的过程进行至少两次，然后进行一次煅烧。在第一次煅烧后形成的电介质薄膜的厚度为20〜600nm。初始煅烧步骤后形成的下部电极的厚度与电介质薄膜的厚度之比（下部电极的厚度/电介质薄膜的厚度）优选在0.10〜15.0的范围内。

66. 发明授权

US08486800B2 Trench capacitor and method for producing the same 失效
标题翻译：沟槽电容器及其制造方法
公开(公告)号：US08486800B2
公开(公告)日：2013-07-16
申请号：US12995452
申请日：2009-05-26
申请人： Jin Liu , Aarnoud Laurens Roest , Freddy Roozeboom , Vahid Shabro
发明人： Jin Liu , Aarnoud Laurens Roest , Freddy Roozeboom , Vahid Shabro
IPC分类号： H01L21/20 , H01L21/8242 , H01L21/336
CPC分类号： H01G4/33 , C23C18/1216 , C23C18/1225 , C23C18/1254 , H01L21/31691 , H01L28/55
摘要： A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance while being efficient in utilization of semiconductor real estate.
摘要翻译：公开了一种制造沟槽电容器的方法，以及由此制造的沟槽电容器。该方法涉及使用真空浸渍方法用于溶胶 - 凝胶膜，以促进高介电常数材料在半导体衬底的沟槽内的有效沉积，以提供具有高电容的沟槽电容器，同时有效地利用半导体房地产。

67. 发明授权

US08486780B2 Doped electrode for dram applications 有权
标题翻译：用于电视应用的掺杂电极
公开(公告)号：US08486780B2
公开(公告)日：2013-07-16
申请号：US13219922
申请日：2011-08-29
申请人： Xiangxin Rui , Hiroyuki Ode
发明人： Xiangxin Rui , Hiroyuki Ode
IPC分类号： H01L21/8242 , H01L21/329
CPC分类号： H01L28/65 , H01L28/40 , H01L28/60
摘要： A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode layers are conductive molybdenum oxide.
摘要翻译：形成用于MIM DRAM电容器的金属氧化物第一电极层，其中第一和/或第二电极层含有一个或多个掺杂剂，直到总掺杂浓度，其将不会阻止电极层在随后的退火步骤期间结晶。一种或多种掺杂剂具有大于约5.0eV的功函数。一种或多种掺杂剂具有小于约1000μmOcm的电阻率。有利地，电极层是导电性氧化钼。

68. 发明授权

US08455322B2 Silicon germanium heterojunction bipolar transistor structure and method 有权
标题翻译：硅锗异质结双极晶体管结构及方法
公开(公告)号：US08455322B2
公开(公告)日：2013-06-04
申请号：US12719212
申请日：2010-03-08
申请人： Oleg Gluschenkov , Rajendran Krishnasamy , Kathryn T. Schonenberg
发明人： Oleg Gluschenkov , Rajendran Krishnasamy , Kathryn T. Schonenberg
IPC分类号： H01L21/8242
CPC分类号： H01L29/66242 , H01L21/2253 , H01L21/26513 , H01L21/324 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/7378
摘要： Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
摘要翻译：公开了一种改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管），其具有窄的基本上无间隙的SIC基座，其外部基极具有最小的重叠。此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。

69. 发明申请

US20130134490A1 LOW RESISTANCE EMBEDDED STRAP FOR A TRENCH CAPACITOR 有权
公开(公告)号：US20130134490A1
公开(公告)日：2013-05-30
申请号：US13307787
申请日：2011-11-30
申请人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
发明人： Karen A. Nummy , Chengwen Pei , Werner A. Rausch , Geng Wang
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L21/4846 , H01L21/82 , H01L27/10867 , H01L29/66181 , H01L29/66636 , H01L29/945
摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

70. 发明授权

US08410535B2 Capacitor and manufacturing method thereof 有权
标题翻译：电容器及其制造方法
公开(公告)号：US08410535B2
公开(公告)日：2013-04-02
申请号：US13093840
申请日：2011-04-25
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L27/108 , H01L29/76 , H01L21/8242
CPC分类号： H01L28/75
摘要： A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.
摘要翻译：提供电容器及其制造方法。电容器包括第一电极，第一金属层，电介质层和第二电极。第一电极设置在基板上。第一金属层设置在第一电极上。电介质层设置在第一金属层上，其中第一金属层的材料不与电介质层的材料反应。第二电极设置在电介质层上。

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