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61. 发明授权

US08898502B2 Clock domain crossing interface 有权
标题翻译：时钟域交叉界面
公开(公告)号：US08898502B2
公开(公告)日：2014-11-25
申请号：US13176160
申请日：2011-07-05
申请人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
发明人： Steven William Maddigan , Dimitri Gabriel Epassa Habib
IPC分类号： G06F1/12 , H04L7/02 , G06F5/10
CPC分类号： G06F1/12 , G06F5/10 , G06F2205/102 , H04L7/005 , H04L7/02
摘要： A flexible and scalable bi-directional CDC interface is set forth between clock domains in a SoC device. The interface comprises a pulse sync circuit for receiving a pulse synchronized to the source clock domain and in response outputting a busy signal to the source clock domain and outputting the pulse synchronized to said destination clock domain; an input register for latching data from said source clock domain in response to a transition of said source clock in the event said busy signal is not active and preventing said data from being latched in the event said busy signal is active so as not to corrupt previously latched data; and an output register for receiving said pulse from said pulse sync circuit and in response latching said pulse from said input register on a transition of said destination clock.
摘要翻译：在SoC设备的时钟域之间提供灵活且可扩展的双向CDC接口。接口包括脉冲同步电路，用于接收与源时钟域同步的脉冲，并且响应于将忙信号输出到源时钟域并输出与所述目的地时钟域同步的脉冲; 输入寄存器，用于在所述忙信号不活动的情况下响应于所述源时钟的转变来锁存来自所述源时钟域的数据，并且在所述忙信号有效的情况下防止所述数据被锁存，以便先前不会损坏锁定数据; 以及输出寄存器，用于从所述脉冲同步电路接收所述脉冲，并且响应于在所述目的地时钟的转变时从所述输入寄存器锁存所述脉冲。

62. 发明授权

US08848848B2 Transmission timing adjustment in radio systems 有权
标题翻译：无线电系统中的发射定时调整
公开(公告)号：US08848848B2
公开(公告)日：2014-09-30
申请号：US12980588
申请日：2010-12-29
申请人： Farshid Nowshadi , Steven Wenham
发明人： Farshid Nowshadi , Steven Wenham
IPC分类号： H04L7/00 , H04L7/02
CPC分类号： H04L7/02
摘要： A method of adjusting the transmission time of a signal in a radio link, the method being performed by a transmitter configured to transmit the signal over the radio link to a receiver and comprising the steps of ascertaining an accuracy that the receiver assumes for the transmitter's clock, calculating an assumed drift of the transmitter's clock based on the assumed accuracy of that clock and the time since a previous correlation between the transmitter's clock and the receiver's clock; and transmitting the signal at a time dependent on the assumed drift.
摘要翻译：一种调整无线电链路中的信号的传输时间的方法，所述方法由被配置为通过无线电链路将信号发送到接收机的发射机执行，并且包括以下步骤：确定接收机为发射机的时钟而准备的精度基于该时钟的假设精度和从发射机的时钟与接收机的时钟之前的相关之后的时间计算发射机时钟的假定漂移; 并根据假定的漂移一次发送信号。

63. 发明授权

US08837639B2 Parallel synchronizing cell with improved mean time between failures 有权
标题翻译：并行同步电池，故障之间的平均时间延长
公开(公告)号：US08837639B2
公开(公告)日：2014-09-16
申请号：US12818219
申请日：2010-06-18
申请人： Ioan Cordos
发明人： Ioan Cordos
IPC分类号： H03K9/06 , H04L7/033 , H04L7/02
CPC分类号： H04L7/0338 , H04L7/02
摘要： In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal.
摘要翻译：在一些实施例中，同步电路包括在比同步电路中的另一同步装置更低的时钟频率下工作的至少一个同步装置。在本发明的至少一个实施例中，一种方法包括以第一频率对第一信号进行采样，从而生成第一信号的多个采样版本。第一频率是将时钟信号除以N的频率。N是大于1的数字。该方法包括以时钟信号的频率采样第二信号。第二信号基于第一信号的多个采样版本中的顺序选择的一个，从而生成第一信号的输出版本。

64. 发明申请

US20140241480A1 HITLESS EFFICIENT TRANSMITTER PROTECTION OF ALL OUTDOOR RADIOS 有权
标题翻译：无害无害的发射机保护所有户外无线电
公开(公告)号：US20140241480A1
公开(公告)日：2014-08-28
申请号：US14342924
申请日：2012-09-10
申请人： ZTE (USA) INC.
发明人： Ying Shen , Andrey Kochetkov
IPC分类号： H04L25/03 , H04L7/00 , H04L7/02
CPC分类号： H04L25/03821 , H04B1/0483 , H04B1/74 , H04L7/0016 , H04L7/02 , H04L27/0014 , H04L2027/0022 , H04L2027/0067 , H04L2027/0087
摘要： A method is provided for synchronizing a first radio unit with a second radio unit associated with an all outdoor radios system, the method including: receiving, at the first radio unit and the second radio unit, respectively, a communication signal from a common communication source; receiving, at the first radio unit and the second radio unit, respectively, a reference signal from a common reference source; synchronizing the communication signal at each of the first radio unit and the second radio unit with the reference signal such that the each of the first radio unit and the second radio unit generates an output signal having substantially the same frequency and substantially the same phase; and transmitting the output signal from each of the first radio unit and the second radio unit to a remote receiver through an antenna.
摘要翻译：提供了一种用于使第一无线电单元与与所有户外无线电系统相关联的第二无线电单元同步的方法，所述方法包括：在第一无线电单元和第二无线电单元处分别从公共通信源接收通信信号 ; 在第一无线电单元和第二无线电单元分别接收来自公共参考源的参考信号; 使用第一无线电单元和第二无线电单元中的每一个的通信信号与参考信号同步，使得第一无线电单元和第二无线电单元中的每一个产生具有基本上相同频率和基本相同相位的输出信号; 并且通过天线将来自第一无线电单元和第二无线电单元中的每一个的输出信号发送到远程接收器。

65. 发明申请

US20140037034A1 METHOD AND SYSTEM FOR MULTI-POINT SIGNAL GENERATION WITH PHASE SYNCHRONIZED LOCAL CARRIERS 有权
标题翻译：多相点信号生成与相位同步本地载波的方法与系统
公开(公告)号：US20140037034A1
公开(公告)日：2014-02-06
申请号：US14049094
申请日：2013-10-08
申请人： Blue Danube Labs, Inc.
发明人： Mihai BANU , Vladimir Ivanov PRODANOV
IPC分类号： H04L7/02
CPC分类号： H04L7/02 , G06F1/12 , H04B15/02 , H04B2215/067
摘要： A method and system of applying modulated carrier signals to tree networks and processing signals tapped from the tree networks to generate output signals with phase-synchronized carriers are disclosed.
摘要翻译：公开了一种将调制载波信号应用于树形网络并处理从树形网络中抽出的信号以产生具有相位同步载波的输出信号的方法和系统。

66. 发明申请

US20140010326A1 Carrier Offset Correction of a Received Signal 有权
标题翻译：接收信号的载波偏移校正
公开(公告)号：US20140010326A1
公开(公告)日：2014-01-09
申请号：US13543481
申请日：2012-07-06
申请人： Sujai Chari
发明人： Sujai Chari
IPC分类号： H04L7/02 , H04B1/14 , H04L27/06
CPC分类号： H04L27/2657 , H04L7/042 , H04L27/0014 , H04L2027/003 , H04L2027/0048 , H04L2027/0095
摘要： Apparatuses, methods and systems for mitigating carrier offset of a received signal are disclosed. One embodiment of a receiver includes a receiver chain operative to receive a communication signal from a desired transmitter, and a controller operative to determine a carrier offset correction based on prior reception of communication signals from the desired transmitter. The receiver chain is operative to generate a carrier offset corrected received signal by applying the carrier offset correction to the received communication signal, and a correlation processor operative to correlate the carrier offset corrected received communication signal with a known sequence.
摘要翻译：公开了用于减轻接收信号的载波偏移的装置，方法和系统。接收机的一个实施例包括可操作以从期望的发射机接收通信信号的接收机链路，以及控制器，用于根据来自所需发射机的通信信号的先前接收来确定载波偏移校正。接收器链可操作以通过对所接收的通信信号应用载波偏移校正来产生载波偏移校正的接收信号，以及相关处理器，用于将载波偏移校正的接收通信信号与已知序列进行相关。

67. 发明授权

US08611485B2 Method and a device for controlling frequency synchronization 有权
标题翻译：方法和用于控制频率同步的装置
公开(公告)号：US08611485B2
公开(公告)日：2013-12-17
申请号：US13477399
申请日：2012-05-22
申请人： Kenneth Hann , Mikko Laulainen
发明人： Kenneth Hann , Mikko Laulainen
IPC分类号： H04L7/02
CPC分类号： H04J3/0664 , H03L7/08
摘要： A device for controlling frequency synchronization includes a processor for controlling a frequency-controlled clock signal on the basis of received timing messages so as to achieve frequency-locking between the frequency-controlled clock signal and a reference clock signal. For the purpose of finding such timing messages which have experienced similar transfer delays and thus are suitable for the frequency control, the processor is configured to control a phase-controlled clock signal on the basis of the timing messages so as to achieve phase-locking between the phase-controlled clock signal and the reference clock signal, and to select the timing messages to be used for the frequency control on the basis of phase-error indicators related to the phase control. Thus, the phase-controlled clock signal is an auxiliary clock signal that is utilized for performing the frequency control.
摘要翻译：用于控制频率同步的装置包括：处理器，用于基于接收到的定时消息来控制频率控制的时钟信号，以便实现频率控制的时钟信号和参考时钟信号之间的频率锁定。为了找到已经经历类似的传输延迟并因此适合于频率控制的定时消息，处理器被配置为基于定时消息来控制相位控制的时钟信号，以便实现相位锁定相位控制时钟信号和参考时钟信号，并且基于与相位控制相关的相位误差指示来选择要用于频率控制的定时消息。因此，相位控制时钟信号是用于执行频率控制的辅助时钟信号。

68. 发明授权

US08611484B2 Receiver having clock recovery unit based on delay locked loop 有权
标题翻译：接收机具有基于延迟锁定环路的时钟恢复单元
公开(公告)号：US08611484B2
公开(公告)日：2013-12-17
申请号：US12920550
申请日：2010-02-09
申请人： Hyun-Kyu Jeon , Yong-Hwan Moon
发明人： Hyun-Kyu Jeon , Yong-Hwan Moon
IPC分类号： H04L7/02
CPC分类号： H03L7/0812 , G09G3/20 , G09G5/008 , G09G2310/027 , G09G2310/08 , G09G2370/08 , H03L7/0807
摘要： A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, includes a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal. The input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level. The clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal.
摘要翻译：一种用于接收周期性地嵌入在数据信号之间的时钟信号的输入信号（时钟嵌入数据（CED）信号）的接收机，包括：时钟恢复单元，被配置为恢复并输出时钟信号;串行/ 并行转换器被配置为恢复和输出数据信号。输入信号（CED信号）包括单电平信号，其中时钟信号周期性地嵌入在相同电平的数据信号之间。时钟恢复单元基于延迟锁定环（DLL）来配置，而不使用用于产生参考时钟信号的内部振荡器。

69. 发明申请

US20130107997A1 CLOCK DATA RECOVERY CIRCUIT 有权
标题翻译：时钟数据恢复电路
公开(公告)号：US20130107997A1
公开(公告)日：2013-05-02
申请号：US13308499
申请日：2011-11-30
申请人： An-Chung Chen
发明人： An-Chung Chen
IPC分类号： H04L7/02
CPC分类号： H03L7/0807 , H03L7/081 , H03L7/093 , H04L7/033
摘要： A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.
摘要翻译：提供具有锁相模块和频率锁定模块的时钟和数据恢复（CDR）电路。锁相模块的相位检测器将输入数据流的相位与数据恢复时钟的相位进行比较，以输出调整信号。频率锁定模块对调整信号执行一阶积分处理和二阶积分处理，以产生第一积分误差和频率控制信号。锁相模块根据第一积分误差和调整信号产生相位控制信号。频率锁定模块的振荡电路根据频率控制信号产生至少一个参考时钟。相位锁定模块的相位转换器根据相位控制信号和参考时钟将数据恢复时钟输出到相位检测器。

70. 发明申请

US20130077723A1 CLOCK-DATA RECOVERY WITH NON-ZERO h(-1) TARGET 有权
标题翻译：时钟数据恢复与非零h（-1）目标
公开(公告)号：US20130077723A1
公开(公告)日：2013-03-28
申请号：US13245533
申请日：2011-09-26
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Osman Javed , Hongtao Zhang
IPC分类号： H04L7/02
CPC分类号： H04L7/0054 , H04L7/0062
摘要： In a receiver circuit, a node receives a signal that carries data from a transmitter circuit. Moreover, a clock-data-recovery (CDR) circuit in the receiver circuit recovers an at-rate clock signal from the received signal. The CDR circuit recovers the clock signal without converging a first pulse-response precursor of the signal relative to a pulse-response cursor of the signal to approximately zero (e.g., with the first pulse-response precursor h(−1) converged to a non-zero value). Furthermore, the first pulse-response precursor corresponds to at least one precurosor or postcursor of the pulse-response other than the current sample.
摘要翻译：在接收机电路中，节点接收从发射机电路传送数据的信号。此外，接收机电路中的时钟数据恢复（CDR）电路从接收到的信号中恢复一个速率时钟信号。 CDR电路恢复时钟信号，而不会将信号的第一脉冲响应前兆相对于信号的脉冲响应光标收敛到大约零（例如，随着第一脉冲响应前兆h（-1）收敛到非零， - 零值）。此外，第一脉冲响应前体对应于除了当前样本以外的脉冲响应的至少一个前体或后脉冲。

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