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71. 发明授权

US5825072A Circuits for ESD Protection of metal to-metal antifuses during processing 失效
标题翻译：处理期间金属对金属反熔丝的ESD保护电路
公开(公告)号：US5825072A
公开(公告)日：1998-10-20
申请号：US599959
申请日：1996-02-14
申请人： Yeochung Yen , Wenn-Jei Chen , Steve S. Chiang , Abdul Rahim Forouhi
发明人： Yeochung Yen , Wenn-Jei Chen , Steve S. Chiang , Abdul Rahim Forouhi
IPC分类号： H01L23/525 , H01L23/60 , H01L29/00
CPC分类号： H01L23/5252 , H01L23/60 , H01L2924/0002
摘要： A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures. A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.
摘要翻译：用于反熔丝的静电保护装置包括比设置在相同的电极间介电层中的反熔丝孔小的面积小的附加的第二尺寸孔。防污材料设置在第二尺寸的孔中，并且上电极在第二孔和第一孔上延伸。用于制造保护装置的优选方法利用形成较小孔径并与形成反熔丝孔同时形成其反熔丝材料层的步骤。用于反熔丝装置的静电保护装置包括具有比第一尺寸的反熔丝孔大的面积的额外的第二尺寸孔。将金属塞材料沉积并回蚀刻。在第一和第二尺寸的孔上形成并限定一层非晶硅反熔丝材料，形成在较大部分填充的反熔丝保护器件单元上的部分较薄。

72. 发明授权

US5789764A Antifuse with improved antifuse material 失效
标题翻译：具有改进的反熔丝材料的防腐剂
公开(公告)号：US5789764A
公开(公告)日：1998-08-04
申请号：US745096
申请日：1996-11-07
申请人： John L. McCollum
发明人： John L. McCollum
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011
摘要： According to the present invention, an antifuse comprises first and second conductors separated by an antifuse material having a thickness selected to impart a desired target programming voltage to the antifuse. The antifuse material is of SiC and provides a solid material stable at temperatures below about 350.degree. C., a resistivity of greater than about 10.sup.12 ohm-cm. The antifuse material may be applied using chemical vapor deposition (CVD) techniques. Also, the SiC antifuse material of the present invention may take any one of a number of via antifuse and stacked antifuse forms.
摘要翻译：根据本发明，反熔丝包括由反熔丝材料隔开的第一和第二导体，所述反熔丝材料具有被选择为向反熔丝赋予期望的目标编程电压的厚度。反熔丝材料是SiC，并且在低于约350℃的温度下提供稳定的固体材料，电阻率大于约1012欧姆 - 厘米。可以使用化学气相沉积（CVD）技术来施加反熔丝材料。此外，本发明的SiC反熔丝材料可以采用多个通孔反熔丝和堆叠的反熔丝形式中的任何一种。

73. 发明授权

US5753528A Method of fabricating metal-to-metal antifuse with improved diffusion barrier layer 失效
标题翻译：用改进的扩散阻挡层制造金属对金属反熔丝的方法
公开(公告)号：US5753528A
公开(公告)日：1998-05-19
申请号：US551835
申请日：1995-11-07
申请人： Abdul R. Forouhi , Iton Wang
发明人： Abdul R. Forouhi , Iton Wang
IPC分类号： H01L21/82 , H01L21/768 , H01L23/522 , H01L23/525 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5252 , H01L23/5256 , H01L2924/0002
摘要： A metal-to-metal antifuse comprises a lower electrode comprising a first metal layer in an integrated circuit, a first barrier layer formed from a layer of TiW:N disposed over the lower electrode, a layer of antifuse material formed from amorphous silicon over the first barrier layer, a second barrier layer formed from a layer of TiW:N disposed over the layer of antifuse material, said second barrier layer, and an upper electrode over the second barrier layer, the upper electrode comprising a second metal layer in the integrated circuit.
摘要翻译：金属对金属反熔丝包括在集成电路中包括第一金属层的下电极，由设置在下电极上的TiW：N层形成的第一势垒层，由非晶硅上形成的反熔丝层，第一阻挡层，由设置在反熔丝层之上的TiW：N层形成的第二阻挡层，所述第二阻挡层和在所述第二阻挡层上的上电极，所述上电极包括所述集成的第二阻挡层中的第二金属层电路。

74. 发明授权

US5741720A Method of programming an improved metal-to-metal via-type antifuse 失效
标题翻译：编制改进的金属对金属通孔型反熔丝的方法
公开(公告)号：US5741720A
公开(公告)日：1998-04-21
申请号：US538962
申请日：1995-10-04
申请人： Frank W. Hawley , Abdelshafy A. Eltoukhy , John L. McCollum
发明人： Frank W. Hawley , Abdelshafy A. Eltoukhy , John L. McCollum
IPC分类号： H01L20060101 , H01L21/70 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having an aluminum-free conductive link. The aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness. In another aspect of the invention, an antifuse having a first barrier metal layer of a first thickness and a second barrier metal layer of a second thickness may be fabricated wherein the first thickness is less than the second thickness and wherein programming of the antifuse is accomplished by placing the more positive voltage of the programming voltage supply on the electrode of the antifuse adjacent the first barrier metal layer.
摘要翻译：设置在CMOS集成电路或类似结构中的两个铝金属化层之间的金属对金属反熔丝包括具有无铝导电连接的反熔丝材料层。通过从具有第一厚度的TiN形成第一阻挡金属层，形成具有第二厚度的第二阻挡金属层，形成第一阻挡金属层，第二厚度可以小于所述第一厚度，第一和第二阻挡金属层将反熔丝材料层与第一和第二电极分离。通过施加能够跨越电极编程反熔丝的电压电位来编程反熔丝，其中施加到邻近具有最小厚度的阻挡金属层的电极的电势的更正的一侧。在本发明的另一方面，可以制造具有第一厚度的第一阻挡金属层和第二厚度的第二阻挡金属层的反熔丝，其中第一厚度小于第二厚度，并且其中完成反熔丝的编程通过将编程电压源的正电压放置在与第一阻挡金属层相邻的反熔丝的电极上。

75. 发明授权

US5633189A Method of making metal to metal antifuse 失效
标题翻译：制造金属对金属反熔丝的方法
公开(公告)号：US5633189A
公开(公告)日：1997-05-27
申请号：US425122
申请日：1995-04-18
申请人： Yeouchung Yen , Shih-Oh Chen
发明人： Yeouchung Yen , Shih-Oh Chen
IPC分类号： H01L23/525 , H01L21/70
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed by means of collimated sputter deposition in the antifuse cell opening to form a layer of uniform thickness existing only within the antifuse cell opening in order to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer and optionally formed by collimated sputter deposition, and a top electrode disposed over the second barrier metal layer.
摘要翻译：本发明的反熔丝结构包括底部平面化电极，设置在底部电极上的ILD，暴露底部电极的ILD中和穿过暴露底部电极的ILD的反熔丝电池，通过反熔丝中的准直溅射沉积设置的第一阻挡金属层电池开口以形成仅在反熔丝电池开口内存在的均匀厚度的层，以便防止反熔丝材料层从底部电极扩散并形成减小面积的有效底部电极，从而降低器件的电容，反熔丝材料层设置在第一阻挡金属层的反熔丝电池开口中，第二阻挡金属层设置在反熔丝材料层上并且任选地通过准直的溅射沉积形成;以及顶部电极，设置在第二阻挡金属层上。

76. 发明授权

US5619063A Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of fabrication 失效
标题翻译：无边界，自对准，差分氧化增强和扩散控制的最小几何反熔丝和制造方法
公开(公告)号：US5619063A
公开(公告)日：1997-04-08
申请号：US646382
申请日：1995-12-12
申请人： Wenn-Jei Chen , Huang-Chung Tseng
发明人： Wenn-Jei Chen , Huang-Chung Tseng
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： The present invention is directed to an antifuse structure and fabrication process wherein the bottom oxide of the ONO antifuse material layer is grown over a small area of N- diffusion surrounded by an N+ diffusion area where the N- diffusion could be patterned as N- "islands" or as N- "stripes", or the like, with the active N- area controlled by the formation and drive-in of the N+ diffusion layer. In this way, the bottom oxide layer of the ONO antifuse material layer is thinner at its center (above the N- region) than at its edges because oxide grows slower on the less doped N- region at the center of the antifuse than at the more heavily doped N+ regions at the edges of the antifuse. Forcing the center of the antifuse material layer to be thinner causes the antifuse to preferentially break down at its center and away from its edges. The opening in the antifuse cell opening mask is wider than the width of the N- diffusion area so that both N- and N+ areas are exposed in the antifuse cell opening step. Since the N+ diffusion can be very accurately dimensionally controlled with known techniques, it is thus possible to reduce the dimension of the active N- diffusion down to 0.2 .mu.m or below, comparing favorably with the linear dimension of 1.0 .mu.m used in currently available state-of-the-art manufacturing processes for antifuses. This represents a factor of 25 reduction in the active antifuse area, which in turn can dramatically reduce the defect density of antifuses over current technology and/or dramatically increase the number of antifuses that may be disposed in a given area of silicon.
摘要翻译：本发明涉及一种反熔丝结构和制造工艺，其中ONO反熔丝层的底部氧化物生长在由N +扩散区域包围的N-扩散区域的小面积上，其中N-扩散区可以被图案化为N-“ 岛“或N”条纹“等，其中活性N区由N +扩散层的形成和驱入控制。以这种方式，ONO反熔丝材料层的底部氧化物层在其中心（在N-区域之上）比在其边缘处更薄，因为在反熔丝的中心处的较少掺杂的N-区域上的氧化物比在在反熔丝边缘处的更重掺杂的N +区域。强制反熔丝材料层的中心较薄会导致反熔丝在其中心处优先分解并远离其边缘。反熔丝电池开口掩模中的开口宽于N-扩散区域的宽度，使得在反熔丝电池打开步骤中都露出N和N +区域。由于N +扩散可以用已知的技术进行精确的尺寸控制，因此可以将活性N-扩散的尺寸减小到0.2μm或更低，与当前可用的1.0μm的线性尺寸相比有利最先进的反熔丝制造工艺。这表示主动反熔丝区域减少了25倍，这反过来可以显着地减少反熔丝超过现有技术的缺陷密度和/或显着增加可以在硅的给定区域中排列的反熔丝的数量。

77. 发明授权

US5614818A Testability circuits for logic circuit arrays 失效
标题翻译：逻辑电路阵列的可测试电路
公开(公告)号：US5614818A
公开(公告)日：1997-03-25
申请号：US303045
申请日：1994-09-08
申请人： Khaled El Ayat , King W. Chan , Theodore M. Speers
发明人： Khaled El Ayat , King W. Chan , Theodore M. Speers
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318516
摘要： A circuit for providing 100% observability and controllability of inputs and outputs of any function circuit module in an array of function circuit modules includes circuitry for placing a test data bit into a selected one of any of the function circuit modules, and circuitry for reading the output of a selected one of any of the function circuit modules.
摘要翻译：用于提供功能电路模块阵列中的任何功能电路模块的输入和输出的100％可观察性和可控性的电路包括用于将测试数据位放置在任何功能电路模块中的选定的一个中的电路，以及用于读取输出任何一个功能电路模块中的一个。

78. 发明授权

US5610534A Logic module for a programmable logic device 失效
标题翻译：可编程逻辑器件的逻辑模块
公开(公告)号：US5610534A
公开(公告)日：1997-03-11
申请号：US505830
申请日：1995-05-18
申请人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
发明人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
IPC分类号： H03K3/037 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K3/037
摘要： A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of n second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth-multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input ere presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.
摘要翻译：逻辑模块包括具有两个数据输入和选择输入的第一和第二多路复用器。两个选择输入都连接到第一类型的双输入逻辑门的输出。第一和第二多路复用器的输入包括来自第一组的数据信号。每个逻辑门的一个输入包括n个第二组的数据信号，并且每个逻辑门的另一个输入包括第三组的数据信号。第三复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入以及连接到第二类型的双输入逻辑门的输出的选择输入。其输出连接到具有耦合到其选择输入的HOLD1输入的第四多路复用器的第一数据输入。其输出和CLEAR输入被呈现给AND门，其输出连接到第四多路复用器的第二数据输入端和第五多路复用器的第一数据输入端。第五多路复用器选择输入包括一个HOLD2输入。其输出和CLEAR输入被提供给AND门，其输出连接到第五多路复用器的第二数据输入端和输出节点。 CLEAR，HOLD1和HOLD2输入包括来自第三组的数据信号的信号的组合，其可以包含其他组之一的数据信号。

79. 发明授权

US5600265A Programmable interconnect architecture 失效
标题翻译：可编程互连体系结构
公开(公告)号：US5600265A
公开(公告)日：1997-02-04
申请号：US575519
申请日：1995-12-20
申请人： Abbas El Gamal , Khaled A. El-Ayat , Amr Mohsen
发明人： Abbas El Gamal , Khaled A. El-Ayat , Amr Mohsen
IPC分类号： G01R31/28 , G01R31/3185 , H01L25/00 , H03K19/177
CPC分类号： G01R31/2884 , G01R31/318516 , G01R31/318519 , H03K19/17704 , H03K19/17736
摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.
摘要翻译：公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。接线通道包括通过常开可编程连接的接线段。位于要连接的任何两个段的交点处的元素。

80. 发明授权

US5525909A Apparatus and method for measuring programmed antifuse resistance 失效
公开(公告)号：US5525909A
公开(公告)日：1996-06-11
申请号：US434396
申请日：1995-05-03
申请人： John L. McCollum
发明人： John L. McCollum
IPC分类号： G01R27/14 , G01R31/28 , G11C17/16 , G11C29/02 , H01L21/66 , G01R31/02
CPC分类号： G11C29/02 , G01R27/14 , G01R31/2884 , G11C17/16 , H01L22/14
摘要： Apparatus for measuring the resistance of a programmed antifuse in an integrated circuit is integrated on the same integrated circuit as the antifuse and is controlled by a programming circuit disposed on an integrated circuit and comprises a first voltage sensing transistor having a first drain/source electrically connected to a first I/O pad, a gate electrically connected to the programming circuit, and a second drain/source electrically connected to a first electrode of the antifuse, and a second voltage sensing transistor having a first drain/source electrically connected to a second I/O pad, a gate electrically connected to the programming circuit, and a second drain/source electrically connected to a second electrode of the antifuse.

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