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1. 发明授权

US08269203B2 Resistive RAM devices for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的电阻式RAM器件
公开(公告)号：US08269203B2
公开(公告)日：2012-09-18
申请号：US12829300
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

2. 发明授权

US5986322A Reduced leakage antifuse structure 失效
标题翻译：减少漏电反熔丝结构
公开(公告)号：US5986322A
公开(公告)日：1999-11-16
申请号：US472050
申请日：1995-06-06
申请人： John L. McCollum , Frank W. Hawley
发明人： John L. McCollum , Frank W. Hawley
IPC分类号： H01L21/82 , H01L23/525 , H01L29/94
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011
摘要： An antifuse comprises an antifuse material disposed between a lower conductive electrode and an upper conductive electrode. The antifuse material comprises a layer of amorphous silicon disposed between two layers of silicon nitride. A thin layer of silicon dioxide is disposed between the layer of amorphous silicon and one of the silicon nitride layers.
摘要翻译：反熔丝包括设置在下导电电极和上导电电极之间的反熔丝材料。反熔丝材料包括设置在两层氮化硅之间的非晶硅层。二氧化硅薄层设置在非晶硅层和氮化硅层之一之间。

3. 发明授权

US5804500A Fabrication process for raised tungsten plug antifuse 失效
标题翻译：高钨钨丝反熔丝的制造工艺
公开(公告)号：US5804500A
公开(公告)日：1998-09-08
申请号：US657971
申请日：1996-06-04
申请人： Frank W. Hawley , John L. McCollum , Ying Go , Abdelshafy Eltoukhy
发明人： Frank W. Hawley , John L. McCollum , Ying Go , Abdelshafy Eltoukhy
IPC分类号： H01L21/82 , H01L23/522 , H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L23/5226 , H01L2924/0002
摘要： An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is formed in the aperture. The upper surface of the interlayer dielectric is etched back to create a raised portion of the plug. The upper edges of the plug are rounded. An antifuse layer, preferably comprising a silicon nitride, amorphous silicon, silicon nitride sandwich incorporating a thin silicon dioxide layer above or below the amorphous silicon layer or such a sandwich structure covered by a titanium nitride layer, is disposed above the plug. An upper electrode, preferably comprising a metal layer is disposed over the antifuse layer.
摘要翻译：反熔丝包括由微电路中的金属层形成的下电极。层间电介质层设置在下电极上并且具有形成在其中的孔。在孔中形成由诸如钨的材料形成的导电插塞。蚀刻层间电介质的上表面以形成插头的凸起部分。插头的上边缘是圆形的。优选地，包括氮化硅，非晶硅，在非晶硅层上方或下方包含薄二氧化硅层的氮化硅夹层或由氮化钛层覆盖的夹层结构的反熔丝层。优选地包括金属层的上电极设置在反熔丝层上。

4. 发明授权

US5614756A Metal-to-metal antifuse with conductive 失效
标题翻译：金属对金属反熔丝导电
公开(公告)号：US5614756A
公开(公告)日：1997-03-25
申请号：US284054
申请日：1994-08-01
申请人： Abdul R. Forouhi , Frank W. Hawley , John L. McCollum , Yeouchung Yen
发明人： Abdul R. Forouhi , Frank W. Hawley , John L. McCollum , Yeouchung Yen
IPC分类号： H01L21/768 , H01L23/525 , H01L23/532 , H01L29/00
CPC分类号： H01L23/5252 , H01L21/76888 , H01L23/53223 , H01L2924/0002
摘要： According to a first aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer under a plug of an electrically conductive material disposed between two metallization layers, According to a second aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer comprising a first nitride/first amorphous silicon/second nitride/second amorphous silicon sandwich under a plug of an electrically conductive material lined with titanium disposed between two metallization layers. In this aspect of the invention the titanium is allowed to react with the second amorphous silicon layer to form an electrically conductive silicide. This leaves the first nitride/first amorphous silicon/second nitride as the antifuse material layer while guaranteeing a strict control on the thickness of the antifuse material layer for assuring strict control over its respective breakdown or programming voltage. According to a third aspect of the present invention an antifuse structure capable of high density fabrication comprises an antifuse material layer disposed over a plug of an electrically conductive material disposed between two metallization layers.
摘要翻译：根据本发明的第一方面，能够进行高密度制造的反熔丝结构包括设置在两个金属化层之间的导电材料的插塞下方的反熔丝材料层。根据本发明的第二方面，提供一种反熔丝结构，高密度制造包括反熔丝材料层，该反熔丝材料层包括第一氮化物/第一非晶硅/第二氮化物/第二非晶硅夹层，所述第一氮化物/第一非晶硅/第二氮化物/第二非晶硅夹层在布置在两个金属化层之间的配有钛的导电材料的插塞下方。在本发明的这个方面，允许钛与第二非晶硅层反应形成导电硅化物。这使得第一氮化物/第一非晶硅/第二氮化物作为反熔丝材料层，同时保证对反熔丝材料层的厚度的严格控制，以确保严格控制其各自的击穿或编程电压。根据本发明的第三方面，能够进行高密度制造的反熔丝结构包括设置在设置在两个金属化层之间的导电材料的插塞之上的反熔丝材料层。

5. 发明授权

US5464790A Method of fabricating an antifuse element having an etch-stop dielectric layer 失效
标题翻译：制造具有蚀刻停止介电层的反熔丝元件的方法
公开(公告)号：US5464790A
公开(公告)日：1995-11-07
申请号：US282145
申请日：1994-07-28
申请人： Frank W. Hawley
发明人： Frank W. Hawley
IPC分类号： H01L21/82 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/525 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5252 , H01L21/76888 , H01L2924/0002
摘要： A dielectric layer through which an antifuse via or an antifuse contact via is to be formed comprises a sandwich of at least two, and preferably three, individual layers. A first etch-stop dielectric layer is disposed over an underlying layer comprising either a lower or upper antifuse electrode barrier layer or an antifuse material layer. The first etch-stop dielectric layer comprises a thin layer of dielectric material. An isolation dielectric layer is disposed over the first etch-stop dielectric layer and comprises a second material comprising most of the thickness of the sandwich and having a substantial etch-time differential from the first etch-stop dielectric material for a selected etchant for the first etch-stop dielectric material. A second etch-stop dielectric layer may be provided under the first etch-stop dielectric layer and may be formed from a third material having a substantial etch time differential from the first etch-stop dielectric material for a selected etchant for the first material. A process for forming a via according to the present invention comprises, in order, the steps of forming the first etch-stop, isolation, masking the sandwich of dielectric layers for formation of a via; etching the isolation dielectric layer with an over-etch, stopping on the underlying first etch-stop dielectric layer; etching the first etch-stop dielectric layer with high over-etch, stopping on the layer beneath it.
摘要翻译：要形成反熔丝通孔或反熔丝接触通孔的电介质层包括至少两个，优选三个单独层的夹层。第一蚀刻停止电介质层设置在包括下反射电抗层或上反电铸阻挡层或反熔丝材料层的下层上。第一蚀刻停止介电层包括介电材料的薄层。隔离电介质层设置在第一蚀刻停止电介质层之上，并且包括第二材料，其包含夹层的大部分厚度，并且与第一蚀刻停留介电材料具有相当的蚀刻 - 时间差，用于所选择的蚀刻剂蚀刻停止电介质材料。可以在第一蚀刻停止介质层下方提供第二蚀刻停止介电层，并且可以由第一材料形成具有与第一蚀刻停止介电材料相当的蚀刻时间差的第三材料，用于第一材料的选定蚀刻剂。根据本发明的用于形成通孔的方法包括以下步骤：形成第一蚀刻停止，隔离，掩蔽介电层的夹层以形成通孔; 用过蚀刻蚀刻隔离介电层，停止在下面的第一蚀刻停止介质层上; 用高过蚀刻蚀刻第一蚀刻停止介质层，停止在其下面的层上。

6. 发明申请

US20130221316A1 FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
标题翻译：前端电阻随机存取存储器
公开(公告)号：US20130221316A1
公开(公告)日：2013-08-29
申请号：US13840815
申请日：2013-03-15
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上方形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

7. 发明授权

US08415650B2 Front to back resistive random access memory cells 有权
标题翻译：从前到后的电阻随机存取存储单元
公开(公告)号：US08415650B2
公开(公告)日：2013-04-09
申请号：US12829311
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory cell is formed on a semiconductor substrate. First and second diffused regions are disposed in the semiconductor substrate. A polysilicon gate is disposed above the first and second diffused regions. A first contact connects the first diffused region with a region of a first metal layer. A first interlayer dielectric layer is formed over the first metal layer and includes first and second vias, each including conductive plugs connected to the region of the first metal layer. First and second resistive random access memory devices formed over the first interlayer dielectric layer have first and second terminals, and include a dielectric layer and an ion source layer. The first terminals of the first and second resistive random access memory devices are coupled to the first metal layer by the first and second conductive plugs.
摘要翻译：电阻性随机存取存储单元形成在半导体衬底上。第一和第二扩散区域设置在半导体衬底中。多晶硅栅极设置在第一和第二扩散区域上方。第一接触将第一扩散区域与第一金属层的区域连接。第一层间电介质层形成在第一金属层之上，并且包括第一和第二通孔，每个通孔包括连接到第一金属层的区域的导电插塞。形成在第一层间介质层上的第一和第二电阻随机存取存储器件具有第一和第二端子，并且包括电介质层和离子源层。第一和第二电阻随机存取存储器件的第一端子通过第一和第二导电插塞耦合到第一金属层。

8. 发明申请

US20110001108A1 FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
标题翻译：前端电阻随机存取存储器
公开(公告)号：US20110001108A1
公开(公告)日：2011-01-06
申请号：US12829311
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

9. 发明授权

US06965156B1 Amorphous carbon metal-to-metal antifuse with adhesion promoting layers 失效
标题翻译：无定形碳金属对金属反熔丝具有粘附促进层
公开(公告)号：US06965156B1
公开(公告)日：2005-11-15
申请号：US10331144
申请日：2002-12-27
申请人： Frank W. Hawley , A. Farid Issaq , John L. McCollum , Shubhra M. Gangopadhyay , Jorge A. Lubguban , Jin Miao Shen
发明人： Frank W. Hawley , A. Farid Issaq , John L. McCollum , Shubhra M. Gangopadhyay , Jorge A. Lubguban , Jin Miao Shen
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S257/903 , H01L2924/00
摘要： A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1+/−0.4, and the ratio of x to y in SixNy is in a range of about 0.75+/−0.225.
摘要翻译：具有下金属电极的金属对金属反熔丝，设置在下金属电极上的下薄增粘层，设置在薄粘附促进层上的无定形碳反应熔剂层，设置在所述反熔丝之上的上薄增粘层材料层和上部金属电极。薄粘附促进层的厚度约为2埃至20埃，并且来自选自包含Si x Si x Si和Si x的组的材料， / SUB> Y 。 Si x x Y y中的x与y的比率在约1 +/- 0.4的范围内，并且Si x N 在约0.75 +/- 0.225的范围内。

10. 发明授权

US5962910A Metal-to-metal via-type antifuse 失效
标题翻译：金属对金属通孔型反熔丝
公开(公告)号：US5962910A
公开(公告)日：1999-10-05
申请号：US895723
申请日：1997-07-17
申请人： Frank W. Hawley , Abdelshafy A. Eltoukhy , John L. McCollum
发明人： Frank W. Hawley , Abdelshafy A. Eltoukhy , John L. McCollum
IPC分类号： H01L20060101 , H01L21/70 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A metal-to-metal antifuse disposed between two aluminum metallization layers in a CMOS integrated circuit or similar structure includes an antifuse material layer having a substantially aluminum-free conductive link. The substantially aluminum-free link is formed by forming a first barrier metal layer out of TiN having a first thickness, a second barrier metal layer out of TiN having a second thickness which may be less than said first thickness, the first and second barrier metal layers separating the antifuse material layer from first and second electrodes. The antifuse is programmed by applying a voltage potential capable of programming the antifuse across the electrodes with the more positive side of the potential applied to the electrode adjacent the barrier metal layer having the least thickness. In another aspect of the invention, an antifuse having a first barrier metal layer of a first thickness and a second barrier metal layer of a second thickness may be fabricated wherein the first thickness is less than the second thickness and wherein programming of the antifuse is accomplished by placing the more positive voltage of the programming voltage supply on the electrode of the antifuse adjacent the first barrier metal layer.
摘要翻译：设置在CMOS集成电路或类似结构中的两个铝金属化层之间的金属对金属反熔丝包括具有基本上不含铝的导电连接的反熔丝材料层。通过从具有第一厚度的TiN形成第一阻挡金属层，形成具有第二厚度的第二阻挡金属层，第二阻挡金属层可以具有小于所述第一厚度，第一和第二阻挡金属将反熔丝材料层与第一和第二电极分离的层。通过施加能够跨越电极编程反熔丝的电压电位来编程反熔丝，其中施加到邻近具有最小厚度的阻挡金属层的电极的电势的更正的一侧。在本发明的另一方面，可以制造具有第一厚度的第一阻挡金属层和第二厚度的第二阻挡金属层的反熔丝，其中第一厚度小于第二厚度，并且其中完成反熔丝的编程通过将编程电压源的正电压放置在与第一阻挡金属层相邻的反熔丝的电极上。

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