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1. 发明授权

US08258811B2 Enhanced field programmable gate array 有权
标题翻译：增强型现场可编程门阵列
公开(公告)号：US08258811B2
公开(公告)日：2012-09-04
申请号：US13158019
申请日：2011-06-10
申请人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

2. 发明申请

US20110234258A1 ENHANCED FILED PROGRAMMABLE GATE ARRAY 有权
标题翻译：增强型可编程门阵列
公开(公告)号：US20110234258A1
公开(公告)日：2011-09-29
申请号：US13158019
申请日：2011-06-10
申请人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

3. 发明授权

US07755386B2 Enhanced field programmable gate array 失效
标题翻译：增强型现场可编程门阵列
公开(公告)号：US07755386B2
公开(公告)日：2010-07-13
申请号：US12111660
申请日：2008-04-29
申请人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

4. 发明授权

US07382155B2 Enhanced field programmable gate array 有权
标题翻译：增强型现场可编程门阵列
公开(公告)号：US07382155B2
公开(公告)日：2008-06-03
申请号：US10916214
申请日：2004-08-10
申请人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： G06F7/38 , H01L27/10
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

5. 发明授权

US6150837A Enhanced field programmable gate array 失效
标题翻译：增强型现场可编程门阵列
公开(公告)号：US6150837A
公开(公告)日：2000-11-21
申请号：US807455
申请日：1997-02-28
申请人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/173 , H03K19/177 , G06F7/38
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

6. 发明授权

US5509128A FPGA architecture including direct logic function circuit to I/O interconnections 失效
标题翻译： FPGA架构包括I / O互连的直接逻辑功能电路
公开(公告)号：US5509128A
公开(公告)日：1996-04-16
申请号：US140724
申请日：1993-10-20
申请人： King W. Chan
发明人： King W. Chan
IPC分类号： H01L27/118 , H01L21/82 , H03K19/177 , G06F13/00
CPC分类号： H03K19/17744 , H03K19/17704
摘要： A user-programmable FPGA architecture includes a plurality of logic function circuits having inputs and outputs disposed on an integrated circuit. A plurality of input/output (I/O) modules are also disposed on the integrated circuit and communicate with I/O pads on the integrated circuit. The I/O modules each include: (1) an input buffer having an input connected to an I/O pad on the integrated circuit and an output connected to an output node, and (2) an output buffer having an input connected to an input node, an output connected to the I/O pad, and a control input connected to a control node for placing the output buffer into a high impedance state. A general interconnect structure disposed on the integrated circuit includes a plurality of interconnect conductors which may be connected to one another, to the inputs and outputs of the logic function circuits, and to the I/O modules by programming user-programmable interconnect elements. Direct interconnections are made between the inputs of selected ones of the logic function circuits and the output nodes of selected ones of the I/O modules. Direct interconnections are made between the outputs of selected ones of the logic function circuits and the input nodes of selected ones of the I/O modules. Direct interconnections are made between the outputs of selected ones of the logic function circuits and the control nodes of selected ones of the I/O modules.
摘要翻译：用户可编程FPGA架构包括多个具有设置在集成电路上的输入和输出的逻辑功能电路。多个输入/输出（I / O）模块也布置在集成电路上并与集成电路上的I / O焊盘通信。 I / O模块各自包括：（1）输入缓冲器，其具有连接到集成电路上的I / O焊盘的输入端和连接到输出节点的输出，以及（2）输出缓冲器，其输入端连接到输入节点，连接到I / O焊盘的输出，以及连接到控制节点的控制输入，用于将输出缓冲器置于高阻抗状态。设置在集成电路上的通用互连结构包括可以彼此连接的多个互连导体，逻辑功能电路的输入和输出，以及通过编程用户可编程的互连元件到I / O模块。在所选择的逻辑功能电路的输入和I / O模块中所选择的输出节点之间进行直接互连。在所选择的逻辑功能电路的输出和所选择的I / O模块的输入节点之间进行直接互连。在所选逻辑功能电路的输出和所选择的I / O模块的控制节点之间进行直接互连。

7. 发明申请

US20100244894A1 ENHANCED FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：增强现场可编程门阵列
公开(公告)号：US20100244894A1
公开(公告)日：2010-09-30
申请号：US12794279
申请日：2010-06-04
申请人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

8. 发明授权

US07389487B1 Dedicated interface architecture for a hybrid integrated circuit 失效
标题翻译：专用于混合集成电路的接口架构
公开(公告)号：US07389487B1
公开(公告)日：2008-06-17
申请号：US09069054
申请日：1998-04-28
申请人： King W. Chan , William C. T. Shu , Sinan Kaptanoglu , Chi Fung Cheng
发明人： King W. Chan , William C. T. Shu , Sinan Kaptanoglu , Chi Fung Cheng
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , G06F15/7867
摘要： An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.
摘要翻译：用于混合IC的接口设计，其利用专用接口轨道来允许信号与FPGA部分的逻辑块分布地接口，从而提供混合IC的FPGA和ASIC部分之间的更快更有效的通信。

9. 发明授权

US06791353B1 Enhanced field programmable gate array 有权
标题翻译：增强型现场可编程门阵列
公开(公告)号：US06791353B1
公开(公告)日：2004-09-14
申请号：US09819084
申请日：2000-09-25
申请人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： G06F738
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

10. 发明授权

US5804960A Circuits for testing the function circuit modules in an integrated circuit 失效
标题翻译：用于测试集成电路中功能电路模块的电路
公开(公告)号：US5804960A
公开(公告)日：1998-09-08
申请号：US722355
申请日：1996-09-27
申请人： Khaled El Ayat , King W. Chan , Theodore M. Speers
发明人： Khaled El Ayat , King W. Chan , Theodore M. Speers
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318516
摘要： A circuit for providing 100% observability and controllability of inputs and outputs of any function circuit module in an array of function circuit modules includes circuitry for placing a test data bit into a selected one of any of the function circuit modules, and circuitry for reading the output of a selected one of any of the function circuit modules.
摘要翻译：用于提供功能电路模块阵列中的任何功能电路模块的输入和输出的100％可观察性和可控性的电路包括用于将测试数据位放置在任何功能电路模块中的选定的一个中的电路，以及用于读取输出任何一个功能电路模块中的一个。

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