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71. 发明申请

US20070130353A1 Link level retry scheme 有权
标题翻译：链路级重试方案
公开(公告)号：US20070130353A1
公开(公告)日：2007-06-07
申请号：US11326982
申请日：2006-01-06
申请人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra Mannava , Rajee Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
发明人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra Mannava , Rajee Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
IPC分类号： G06F15/16
CPC分类号： H04L1/188 , H04L1/1614 , H04L1/1671 , H04L1/1874 , H04L29/06 , H04L69/324 , H04L2001/125
摘要： A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
摘要翻译：提供了一个链路层系统。链路层系统是第一链路层控制模块和用于存储传输的数据分组的重试队列。重试控制模块耦合到第一链路层控制模块，当第一链路层控制模块接收到确认位时，引导重试队列丢弃所发送的数据分组。

72. 发明授权

US07167957B2 Mechanism for handling explicit writeback in a cache coherent multi-node architecture 有权
标题翻译：在缓存一致多节点架构中处理显式回写的机制
公开(公告)号：US07167957B2
公开(公告)日：2007-01-23
申请号：US10896151
申请日：2004-07-20
申请人： Manoj Khare , Lily P. Looi , Akhilesh Kumar
发明人： Manoj Khare , Lily P. Looi , Akhilesh Kumar
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0828
摘要： A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.
摘要翻译：描述了一种用于在高速缓存相关多节点架构中处理显式回写的机制的方法和装置。在一个实施例中，本发明是一种方法。该方法包括在相干存储器系统中接收与第一行数据有关的读取请求。该方法还包括在接收到读取请求的同时接收与第一行数据相关的写入请求。该方法还包括检测读请求和写请求都与第一行相关。该方法还包括确定读和写请求的哪个请求应首先进行。此外，该方法包括完成应该首先进行的读取和写入请求的请求。

73. 发明授权

US07124252B1 Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system 有权
标题翻译：用于将有序输入/输出事务流水线分配存储器，高速缓存一致的多处理器系统中的相干存储器的方法和装置
公开(公告)号：US07124252B1
公开(公告)日：2006-10-17
申请号：US09643380
申请日：2000-08-21
申请人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Kenneth C. Creta
发明人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Kenneth C. Creta
IPC分类号： G06F13/14
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/0835
摘要： An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.
摘要翻译：用于将有序输入/输出事务流水线分配到分布式存储器，高速缓存一致的多处理器系统中的相干存储器的方法。响应于来自指向分布式相干存储器的输入/输出总线的事务，预取引擎从分布式相干存储器预取数据。输入/输出相干缓存缓冲器接收预取数据，并与分布式，相干存储器和系统中的其他高速缓存代理保持一致。

74. 发明申请

US20060126656A1 Method, system, and apparatus for system level initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US20060126656A1
公开(公告)日：2006-06-15
申请号：US11011801
申请日：2004-12-13
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur Jayasimha , Murugasamy Nachimuthu , Phanindra Mannava
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur Jayasimha , Murugasamy Nachimuthu , Phanindra Mannava
IPC分类号： H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

75. 发明授权

US06976129B2 Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture 有权
标题翻译：用于将已知事务长度的I / O事务处理到缓存一致多节点体系结构中的相干内存的机制
公开(公告)号：US06976129B2
公开(公告)日：2005-12-13
申请号：US10261944
申请日：2002-09-30
申请人： Kenneth C. Creta , Manoj Khare , Lily P. Looi , Akhilesh Kumar
发明人： Kenneth C. Creta , Manoj Khare , Lily P. Looi , Akhilesh Kumar
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0813 , Y10S707/99952
摘要： A method and apparatus for a mechanism for handling i/o transactions with known transaction length to coherent memory in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a request for a current copy of a data line. The method further includes finding the data line within a cache-coherent multi-node system. The method also includes copying the data line without disturbing a state associated with the data line. The method also includes providing a copy of the data line in response to the request. The method also includes determining if the data line is a last data line of a transaction based on a known transaction length of the transaction.
摘要翻译：描述了一种用于处理具有已知事务长度的I / O事务的机制的方法和装置，用于缓存相关多节点架构中的相干存储器。在一个实施例中，本发明是一种方法。该方法包括接收对数据线的当前副本的请求。该方法还包括在高速缓存相干多节点系统内找到数据线。该方法还包括复制数据线而不干扰与数据线相关联的状态。该方法还包括响应于该请求提供数据线的副本。该方法还包括基于事务的已知事务长度来确定数据行是否是事务的最后数据行。

76. 发明申请

US20050204193A1 Dynamic interconnect width reduction to improve interconnect availability 有权
标题翻译：动态互连宽度减少，以提高互连可用性
公开(公告)号：US20050204193A1
公开(公告)日：2005-09-15
申请号：US10801448
申请日：2004-03-12
申请人： Phanindra Mannava , Victor Lee , Akhilesh Kumar , Doddaballapur Jayasimha , Ioannis Schoinas
发明人： Phanindra Mannava , Victor Lee , Akhilesh Kumar , Doddaballapur Jayasimha , Ioannis Schoinas
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/1443 , G06F11/2007 , G06F2213/0038 , H04L1/1867 , H04L2001/0094
摘要： In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，一种装置包括传输错误检测器，用于响应于检测到的错误来检测互连的传输错误和发送代理重试传输。如果重试不成功，该装置还包括硬故障检测器，用于检测互连的硬故障;以及传输宽度减小器，以响应于硬故障检测器来减小互连的传输宽度。描述和要求保护其他实施例。

77. 发明申请

US20050144488A1 Method and apparatus of lowering I/O bus power consumption 审中-公开
标题翻译：降低I / O总线功耗的方法和装置
公开(公告)号：US20050144488A1
公开(公告)日：2005-06-30
申请号：US10810119
申请日：2004-03-25
申请人： Victor Lee , Phanindra Mannava , Akhilesh Kumar , Sanjay Dabral
发明人： Victor Lee , Phanindra Mannava , Akhilesh Kumar , Sanjay Dabral
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3209 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： The current method and apparatus provides a novel approach to manage the power consumption of a high speed I/O interface by selectively turning off non-essential portions of the interface. Here only part of the interface is powered off as compared to the whole interface being turned off. From the upper layers (protocol/system) perspective, the interface is always “on”. Thus, this mechanism reduces link power by selectively turning off portions of the link, yet allowing for fast wake up in an interface power management architecture.
摘要翻译：目前的方法和装置提供了一种新颖的方法，通过选择性地关闭界面的非必要部分来管理高速I / O接口的功耗。与整个接口关闭相比，这里只有部分接口掉电。从上层（协议/系统）的角度来看，界面总是“开”。因此，该机制通过选择性地关闭链路的部分而减少链路功率，但允许在接口电源管理架构中快速唤醒。

78. 发明授权

US06859864B2 Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line 失效
标题翻译：响应于读取或窥探修改的高速缓存行启动隐式回写的机制
公开(公告)号：US06859864B2
公开(公告)日：2005-02-22
申请号：US09752576
申请日：2000-12-29
申请人： Manoj Khare , Lily P. Looi , Akhilesh Kumar , Kenneth C. Creta
发明人： Manoj Khare , Lily P. Looi , Akhilesh Kumar , Kenneth C. Creta
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0804 , G06F12/082 , G06F12/0831
摘要： A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that another node other than the requesting node and the home node for the desired data has a copy of the data. The switch directs the request to the responding node that is not the home node. The responding node, having modified the data, provides a single response back to the switch that causes the switch to both update the data at the home node and answer the requesting node. The updating of the data at the home node is done without receiving an explicit write instruction from the requesting node.
摘要翻译：描述了一种用于在实现基于窥探的体系结构的分布式共享存储器环境中提供隐式回写的方法和装置。请求节点向基于窥探的架构控制器交换机提交单个读取请求。该交换机识别除请求节点之外的另一节点和所需数据的归属节点具有该数据的副本。交换机将请求引导到不是主节点的响应节点。已经修改了数据的响应节点向交换机提供了一个单一的响应，该响应使交换机能够更新归属节点处的数据并且回答请求节点。在家庭节点处的数据更新完成，而不从请求节点接收到明确的写入指令。

79. 发明授权

US06660696B1 Thermally stable phosphorothionates as antioxidant, antiwear, friction reducing and extreme pressure lubricant additives from cashew nut shell liquid 有权
标题翻译：热稳定的硫代磷酸酯作为抗氧化剂，抗磨损，降低摩擦力和从腰果壳液中极压润滑剂添加剂
公开(公告)号：US06660696B1
公开(公告)日：2003-12-09
申请号：US10189374
申请日：2002-06-20
申请人： Rajeev Ranjan , Ajay Kumar Arora , Rakesh Sarin , Deepak Kumar Tuli , Ram Prakash Verma , Akhilesh Kumar Bhatnagar
发明人： Rajeev Ranjan , Ajay Kumar Arora , Rakesh Sarin , Deepak Kumar Tuli , Ram Prakash Verma , Akhilesh Kumar Bhatnagar
IPC分类号： C10M13710
CPC分类号： C10M169/04 , C07F9/18 , C10M137/10 , C10M169/00 , C10M2223/047 , C10N2210/01 , C10N2210/02 , C10N2210/04 , C10N2230/06 , C10N2230/10
摘要： Phosphorothionate derivatives derived from cashew nut shell liquid (CNSL) for use as an thermally stable antioxidant, antiwear, friction reducing and extreme pressure additive in a lubricant composition are synthesized by the steps of (a) partially hydrogenating distilled technical cashew nut shell liquid with palladium or nickel or platinum catalyst; to hydrogenate the olefinic chain; (b) reacting partially hydrogenated technical cashew nut shell liquid with phosphorus trihalide and sulphur, the reaction being carried out at a temperature ranging from 20 to 220° C. A lubricant containing a major proportion of a material selected from the group consisting of an oil of lubricating viscosity or a grease; and remainder an additive including CNSL phosphorothionate derivative, prepared by the foregoing process.
摘要翻译：衍生自腰果壳液（CNSL）的硫代磷酸衍生物用作润滑剂组合物中的热稳定抗氧化剂，抗磨损，减摩和极压添加剂，是通过以下步骤合成的：（a）将蒸馏的技术腰果壳液与钯或镍或铂催化剂; 氢化烯烃链; （b）使部分氢化的技术腰果壳液与三卤化磷和硫反应，反应在20-220℃的温度下进行。含有主要比例的选自以下的材料的润滑剂：油的润滑粘度或润滑脂; 其余为通过上述方法制备的包括CNSL硫代磷酸酯衍生物的添加剂。

80. 发明授权

US06622215B2 Mechanism for handling conflicts in a multi-node computer architecture 失效
公开(公告)号：US06622215B2
公开(公告)日：2003-09-16
申请号：US09753263
申请日：2000-12-29
申请人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Sin S. Tan
发明人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Sin S. Tan
IPC分类号： G06F1200
CPC分类号： G06F12/0828 , G06F12/0813 , G06F12/082 , G06F12/0831
摘要： According to one embodiment, a method is disclosed. The method includes receiving a first request from a first node in a multi-node computer system to invalidate a first cache line at a second node. The method also includes receiving a second request from the second node to invalidate the first cache line at the first node and detecting the concurrent requests at conflict detection circuitry.

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