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71. 发明授权

US4914496A Gate turn-off thyristor with independent turn-on/off controlling transistors 失效
标题翻译：具有独立导通/截止控制晶体管的栅极截止晶闸管
公开(公告)号：US4914496A
公开(公告)日：1990-04-03
申请号：US157584
申请日：1988-02-19
申请人： Akio Nakagawa , Takashi Shinohe
发明人： Akio Nakagawa , Takashi Shinohe
IPC分类号： H01L29/74 , H01L29/745 , H01L29/749
CPC分类号： H01L29/7455 , H01L29/7428 , H01L29/749
摘要： A gate turn-off thyristor has first and second MOSFETs serving as turn-on and turn-off controlling devices, respectively. A p type semiconductor layer is additionally formed in an n type substrate functioning as a first base in such a manner as to overlap a p type second base layer. The additional layer is different from the second base in impurity concentration, thereby causing the resistivity of the second base to be smaller than that of the additional layer. The first MOSFET has an n type source layer formed in the additional layer to define a surface portion of the additional layer positioned between the source layer and the first base layer as a channel region of the first MOSFET. A turn-on gate layer is provided to cover a surface region of the first base and the channel region of the first MOSFET.

72. 发明授权

US4700466A Method of manufacturing semiconductor device wherein silicon substrates are bonded together 失效
标题翻译：制造半导体器件的方法，其中硅衬底结合在一起
公开(公告)号：US4700466A
公开(公告)日：1987-10-20
申请号：US825544
申请日：1986-02-03
申请人： Akio Nakagawa , Hiromichi Ohashi , Tsuneo Ogura , Masaru Shimbo
发明人： Akio Nakagawa , Hiromichi Ohashi , Tsuneo Ogura , Masaru Shimbo
IPC分类号： H01L29/78 , H01L21/02 , H01L21/18 , H01L21/20 , H01L21/306 , H01L21/336 , H01L27/12 , H01L29/74 , H01L29/861 , H01L21/461
CPC分类号： H01L21/02052 , H01L21/187
摘要： A method of manufacturing a semiconductor device, wherein a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer is formed. A first silicon substrate, having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, is brought into contact with a second silicon substrate which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other. The contacting substrates are then placed in a clean atmosphere so that virtually no foreign substances are present therebetween, and annealed at a temperature of not less than 200.degree. C. so as to bond them together, thereby forming the second impurity-doped layer consisting of the third impurity doped layer and the second silicon substrate.
摘要翻译：一种制造半导体器件的方法，其中形成具有第一杂质掺杂层和杂质浓度高于第一杂质掺杂层的第二杂质掺杂层的半导体晶片。具有第一杂质掺杂层和第三杂质掺杂层的第一硅衬底，其具有比第一杂质掺杂层高的杂质浓度和与第二杂质掺杂层相同的导电类型，以及其表面经镜面抛光与第二硅衬底接触，第二硅衬底的杂质浓度高于第一杂质掺杂层的杂质浓度并且具有与第二杂质掺杂层相同的导电类型，并且其表面为镜面抛光，使得其镜面抛光表面彼此接触。然后将接触的基材放置在清洁的气氛中，实际上不存在异物，并在不低于200℃的温度下进行退火，以将它们结合在一起，由此形成第二杂质掺杂层，由第三杂质掺杂层和第二硅衬底。

73. 发明授权

US4243999A Gate turn-off thyristor 失效
标题翻译：门极关断晶闸管
公开(公告)号：US4243999A
公开(公告)日：1981-01-06
申请号：US58128
申请日：1979-07-16
申请人： Makoto Azuma , Akio Nakagawa
发明人： Makoto Azuma , Akio Nakagawa
IPC分类号： H01L29/10 , H01L29/36 , H01L29/74 , H01L29/744 , H01L29/747
CPC分类号： H01L29/36 , H01L29/102 , H01L29/7416 , H01L29/7432 , H01L29/744 , H01L29/747
摘要： A gate turn-off thyristor which comprises a semiconductor body having at least four contiguous layers, namely, a first layer of a first conductivity type, a second layer lying continguous to the first layer and having a second conductivity type, a third layer lying contiguous to the second layer and having said first conductivity type, and a fourth layer contiguous to the third layer and having said conductivity type;an anode electrode mounted on said first layer;a gate electrode formed on said third layer; anda cathode electrode deposited on said fourth layer, and in which the following two relations are satisfied:.rho..multidot.V.sub.j /.rho..sub.sb .gtoreq. 10.5(v.multidot.cm) and .rho..sub.sb .ltoreq. 35 (.OMEGA./ )where .rho..sub.sb = sheet resistance (.OMEGA./ ) at the normal temperature of the third layer, V.sub.j = backward withstanding voltage (V) at a PN junction bertween the third and fourth layers, and .rho. = specific resistance (.OMEGA..multidot.cm) of the second layer.
摘要翻译：一种栅极截止晶闸管，包括具有至少四个相邻层的半导体本体，即第一导电类型的第一层，与第一层相邻并具有第二导电类型的第二层，邻接的第三层具有所述第一导电类型的第二层和与所述第三层邻接且具有所述导电类型的第四层; 安装在所述第一层上的阳极; 形成在所述第三层上的栅电极; 和沉积在所述第四层上的阴极，其中满足以下两个关系：rho xVj / rho sb> / = 10.5（vxcm）和rho sb

74. 发明授权

US08411988B2 Image processing apparatus and method for managing margin data 有权
标题翻译：用于管理保证金数据的图像处理装置和方法
公开(公告)号：US08411988B2
公开(公告)日：2013-04-02
申请号：US12179043
申请日：2008-07-24
申请人： Akio Nakagawa , Hisashi Ishikawa
发明人： Akio Nakagawa , Hisashi Ishikawa
IPC分类号： G06K9/40
CPC分类号： H04N1/3876 , H04N1/40
摘要： An image processing apparatus partitions entered image data into first partitioned image data and appends margin data to the first partitioned image data. The image processing apparatus corrects the first partitioned image data other than the margin data to second partitioned image data and processes the second partitioned image data and the margin data.
摘要翻译：图像处理装置将输入的图像数据分割成第一分割图像数据，并将余量数据附加到第一分割图像数据。图像处理装置将除了边缘数据之外的第一分割图像数据修正为第二分割图像数据，并处理第二分割图像数据和边缘数据。

75. 发明申请

US20110102040A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20110102040A1
公开(公告)日：2011-05-05
申请号：US12986500
申请日：2011-01-07
申请人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： H03K3/017
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

76. 发明授权

US07893744B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07893744B2
公开(公告)日：2011-02-22
申请号：US12351426
申请日：2009-01-09
申请人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： H03K3/017
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

77. 发明授权

US07868418B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07868418B2
公开(公告)日：2011-01-11
申请号：US12050822
申请日：2008-03-18
申请人： Akio Nakagawa
发明人： Akio Nakagawa
IPC分类号： H01L29/06
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66727
摘要： A first main electrode is provided on one surface thereof. On the other surface thereof, a second semiconductor layer of the first conduction type and a third semiconductor layer of the second conduction type are arranged alternately along the surface. A fourth semiconductor layer of the second conduction type and a fifth semiconductor layer of the first conduction type are stacked on the surfaces of the second and third semiconductor layers. The semiconductor device further comprises a control electrode formed in a trench with an insulator interposed therebetween. The trench passes through the fourth and fifth semiconductor layers and reaches the second semiconductor layer. A sixth semiconductor layer of the first conduction type is diffused from the bottom of the trench. A second main electrode is connected to the fourth and fifth semiconductor layers.
摘要翻译：第一主电极设置在其一个表面上。在其另一个表面上，第一导电类型的第二半导体层和第二导电类型的第三半导体层沿表面交替布置。第二导电类型的第四半导体层和第一导电类型的第五半导体层堆叠在第二和第三半导体层的表面上。半导体器件还包括形成在沟槽中的控制电极，绝缘体插入其间。沟槽穿过第四和第五半导体层并到达第二半导体层。第一导电类型的第六半导体层从沟槽的底部扩散。第二主电极连接到第四和第五半导体层。

78. 发明授权

US07821043B2 Insulated gate bipolar transistor 有权
标题翻译：绝缘栅双极晶体管
公开(公告)号：US07821043B2
公开(公告)日：2010-10-26
申请号：US11763558
申请日：2007-06-15
申请人： Akio Nakagawa
发明人： Akio Nakagawa
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L29/0834 , H01L29/36
摘要： An insulated gate bipolar transistor has a p-type emitter layer; an n-type buffer layer provided on the p-type emitter layer; an n-type base layer provided on the n-type buffer layer and having a higher resistivity than the n-type buffer layer; a p-type base layer provided in part of an upper surface of the n-type base layer; an n-type source layer provided in part of an upper surface of the p-type base layer; a trench extending through the n-type source layer and the p-type base layer to the n-type base layer; a gate electrode provided in the trench; and a gate insulating film provided between the gate electrode and an inner surface of the trench. The p-type emitter layer has a thickness of 5 to 50 μm and a dopant concentration of 2×1016 to 1×1018 cm−3.
摘要翻译：绝缘栅双极晶体管具有p型发射极层; 设置在p型发射极层上的n型缓冲层; 设置在n型缓冲层上并具有比n型缓冲层更高的电阻率的n型基极层; 设置在n型基底层的上表面的一部分的p型基底层; 设置在p型基底层的上表面的一部分的n型源极层; 通过n型源极层和p型基极层延伸到n型基极层的沟槽; 设置在沟槽中的栅电极; 以及栅极绝缘膜，设置在所述栅电极和所述沟槽的内表面之间。 p型发射极层的厚度为5〜50μm，掺杂浓度为2×1016〜1×1018cm-3。

79. 发明申请

US20090179681A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090179681A1
公开(公告)日：2009-07-16
申请号：US12351426
申请日：2009-01-09
申请人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： G06F1/04
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

80. 发明申请

US20090034861A1 IMAGE PROCESSING APPARATUS AND METHOD 有权
标题翻译：图像处理装置和方法
公开(公告)号：US20090034861A1
公开(公告)日：2009-02-05
申请号：US12179043
申请日：2008-07-24
申请人： Akio Nakagawa , Hisashi Ishikawa
发明人： Akio Nakagawa , Hisashi Ishikawa
IPC分类号： G06K9/40 , H04N1/04
CPC分类号： H04N1/3876 , H04N1/40
摘要： An image processing apparatus partitions entered image data into first partitioned image data and appends margin data to the first partitioned image data. The image processing apparatus corrects the first partitioned image data other than the margin data to second partitioned image data and processes the second partitioned image data and the margin data.
摘要翻译：图像处理装置将输入的图像数据分割成第一分割图像数据，并将余量数据附加到第一分割图像数据。图像处理装置将除了边缘数据之外的第一分割图像数据修正为第二分割图像数据，并处理第二分割图像数据和边缘数据。

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