专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08608162B2 Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US08608162B2
公开(公告)日：2013-12-17
申请号：US13434175
申请日：2012-03-29
申请人： Kazutoshi Nakamura , Takashi Saito
发明人： Kazutoshi Nakamura , Takashi Saito
IPC分类号： B65H31/26
CPC分类号： B41J13/106 , B65H31/26 , B65H2402/46 , B65H2404/63 , B65H2405/1114 , B65H2801/06 , G03G15/6552
摘要： An image forming apparatus including an image forming unit, a discharger, and a presser including a swingable member and a contact member is provided. The contact member is partially attached to the swingable member in a condition to create clearance between an unattached part and the swingable member. Weights of the contact member and the swingable member affect the sheet when the recording medium contacts the contact member and the contact member is moved to swing upward along with the swingable member by the recording medium. Resilient force is provided by the contact member to affect the recording medium when the recording medium contacts the contact member and the contact member is moved in a direction to narrow the clearance.
摘要翻译：提供一种包括图像形成单元，放电器和包括可摆动构件和接触构件的按压器的图像形成设备。接触构件在形成未连接部分和可摆动构件之间的间隙的状态下部分地附接到可摆动构件。当记录介质接触接触构件时，接触构件和可摆动构件的重量影响片材，并且接触构件通过记录介质与可摆动构件一起向上移动。当记录介质接触接触构件并且接触构件沿使间隙变窄的方向移动时，接触构件提供弹性力以影响记录介质。

2. 发明申请

US20120256607A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120256607A1
公开(公告)日：2012-10-11
申请号：US13527678
申请日：2012-06-20
申请人： Kazutoshi NAKAMURA , Toru TAKAYAMA , Yuki KAMATA , Akio NAKAGAWA , Yoshinobu SANO , Toshiyuki NAKA
发明人： Kazutoshi NAKAMURA , Toru TAKAYAMA , Yuki KAMATA , Akio NAKAGAWA , Yoshinobu SANO , Toshiyuki NAKA
IPC分类号： G05F1/00
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

3. 发明申请

US20120013316A1 DC-DC CONVERTER 审中-公开
标题翻译： DC-DC转换器
公开(公告)号：US20120013316A1
公开(公告)日：2012-01-19
申请号：US13053517
申请日：2011-03-22
申请人： Kazutoshi Nakamura , Daisuke Minohara
发明人： Kazutoshi Nakamura , Daisuke Minohara
IPC分类号： G05F1/00
CPC分类号： H02M3/00 , H01L23/50 , H01L23/64 , H01L24/14 , H01L24/17 , H01L27/0617 , H01L2224/14134 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： According to one embodiment, a DC-DC converter includes a mounting substrate and a semiconductor device. The semiconductor device includes a first switch element, a second switch element, a first interconnect layer receiving an input potential, a second interconnect layer connected with an inductor, a third interconnect layer receiving a reference potential, and a fourth interconnect layer connected with the inductor. These layers are disposed side by side in one direction on one layer. The mounting substrate includes a fifth interconnect pattern receiving an input potential and disposed adjacently on one side of a mounting region of the semiconductor device, a sixth interconnect pattern receiving a reference voltage and disposed adjacently on the one side of the mounting region, and a seventh interconnect pattern disposed adjacently on one other side opposite to the one side of the mounting region.
摘要翻译：根据一个实施例，DC-DC转换器包括安装基板和半导体器件。半导体器件包括第一开关元件，第二开关元件，接收输入电位的第一互连层，与电感器连接的第二互连层，接收参考电位的第三互连层，以及与电感器连接的第四互连层。这些层在一个层上沿一个方向并排布置。安装基板包括接收输入电位并相邻地设置在半导体器件的安装区域的一侧上的第五布线图案，接收参考电压并相邻布置在安装区域的一侧上的第六布线图案，以及第七布线图案互连图案相邻设置在与安装区域的一侧相对的另一侧上。

4. 发明申请

US20110221409A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110221409A1
公开(公告)日：2011-09-15
申请号：US13110971
申请日：2011-05-19
申请人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi NAKAMURA , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： G05F1/00 , H03H11/26
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

5. 发明申请

US20110133818A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110133818A1
公开(公告)日：2011-06-09
申请号：US13022611
申请日：2011-02-07
申请人： Tomoko MATSUDAI , Norio Yasuhara , Kazutoshi Nakamura
发明人： Tomoko MATSUDAI , Norio Yasuhara , Kazutoshi Nakamura
IPC分类号： H03K3/01 , H01L29/78
CPC分类号： H01L29/7835 , H01L21/266 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.
摘要翻译：半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

6. 发明申请

US20110109287A1 SEMICONDUCTOR PACKAGE AND DC-DC CONVERTER 审中-公开
标题翻译：半导体封装和直流 - 直流转换器
公开(公告)号：US20110109287A1
公开(公告)日：2011-05-12
申请号：US12886898
申请日：2010-09-21
申请人： Kazutoshi Nakamura , Daisuke Minohara
发明人： Kazutoshi Nakamura , Daisuke Minohara
IPC分类号： G05F1/10 , H01L23/495
CPC分类号： H01L23/49562 , H01L23/3107 , H01L23/36 , H01L23/4824 , H01L23/49524 , H01L23/49575 , H01L24/16 , H01L24/40 , H01L24/49 , H01L2224/0603 , H01L2224/16 , H01L2224/16245 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/83801 , H01L2924/00014 , H01L2924/014 , H01L2924/13091 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： According to one embodiment, a semiconductor package includes a chip, a plurality of bumps, a source frame, a drain frame, and a mold member. The chip has a lateral transistor formed inside the chip and has a top source electrode exposed on a first surface of the chip and a top drain electrode exposed on the first surface of the chip. The plurality of bumps are mounted on each of the top source electrode and the top drain electrode. The source frame is connected to the top source electrode through the bumps. The drain frame is connected to the top drain electrode through the bumps. The mold member embeds at least a part of each of the chip, the bumps, the source frame and the drain frame.
摘要翻译：根据一个实施例，半导体封装包括芯片，多个凸块，源框架，排水框架和模具构件。芯片具有形成在芯片内部的横向晶体管，并且具有暴露在芯片的第一表面上的顶部源电极和暴露在芯片的第一表面上的顶部漏电极。多个凸块安装在顶部源电极和顶部漏电极中的每一个上。源框架通过凸块连接到顶部源极电极。漏极框架通过凸块连接到顶部漏极电极。模具构件嵌入芯片，凸块，源框架和排水框架中的每一个的至少一部分。

7. 发明申请

US20110031952A1 SEMICONDUCTOR APPARATUS AND POWER SOURCE CIRCUIT 审中-公开
标题翻译：半导体器件和电源电路
公开(公告)号：US20110031952A1
公开(公告)日：2011-02-10
申请号：US12851396
申请日：2010-08-05
申请人： Kazutoshi NAKAMURA
发明人： Kazutoshi NAKAMURA
IPC分类号： G05F1/10 , H01L27/088
CPC分类号： H01L21/823425 , H01L21/823475 , H01L27/088 , H02M3/1588 , Y02B70/1466
摘要： According to one embodiment, a semiconductor apparatus includes a substrate, a semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type, a first main electrode, a second semiconductor layer of the second conductivity type, a third semiconductor layer of the first conductivity type, a second main electrode, a gate insulating film, and a gate electrode. An electron injected from the first semiconductor region into the semiconductor layer is recombined with an electron hole injected from the third semiconductor region into the semiconductor layer in a state of a body diode is biased in a forward direction. The body diode includes the semiconductor layer, the first semiconductor region, and the third semiconductor region.
摘要翻译：根据一个实施例，半导体装置包括基板，第一导电类型的半导体层，第二导电类型的第一半导体区域，第一主电极，第二导电类型的第二半导体层，第三半导体层的第一导电类型，第二主电极，栅极绝缘膜和栅电极。将从第一半导体区域注入到半导体层中的电子与从第三半导体区域注入到半导体层中的电子空穴与身体二极管的状态向正方向偏置。体二极管包括半导体层，第一半导体区域和第三半导体区域。

8. 发明授权

US07675757B2 DC-DC converter 有权
标题翻译： DC-DC转换器
公开(公告)号：US07675757B2
公开(公告)日：2010-03-09
申请号：US11447115
申请日：2006-06-06
申请人： Kazutoshi Nakamura
发明人： Kazutoshi Nakamura
IPC分类号： H02M3/00 , H02M7/00
CPC分类号： H02M3/156 , H02M3/1588 , H02M2001/0009 , Y02B70/1466
摘要： Disclosed is a DC-DC converter including: a first switching element ON/OFF controlling a current fed from a primary side to a secondary side; a second switching element provided in parallel to the first switching element, controlled at a substantially same timing as an ON/OFF timing of the first switching element and being lower in current rating than the first switching element; and a resistance inserted and connected between a node of a primary side of the second switching element and the primary side of the first switching element.
摘要翻译：公开了一种DC-DC转换器，包括：第一开关元件ON / OFF，其控制从初级侧向次级侧馈送的电流; 与第一开关元件并联设置的第二开关元件，以与第一开关元件的接通/断开定时基本相同的时刻被控制，并且电流额定值低于第一开关元件; 以及插入并连接在第二开关元件的初级侧的节点和第一开关元件的初级侧之间的电阻。

9. 发明授权

US07554160B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07554160B2
公开(公告)日：2009-06-30
申请号：US11333281
申请日：2006-01-18
申请人： Kazutoshi Nakamura
发明人： Kazutoshi Nakamura
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L27/0251 , H01L29/1083 , H01L29/7302 , H01L29/7393 , H01L29/7835
摘要： A semiconductor device has a source region, a channel region and a drain region formed in order along a surface of a substrate, a vertical type bipolar transistor formed from the source region below the substrate, a base contact region of the vertical type bipolar transistor, a buried layer connected to the vertical type bipolar transistor, a buried contact layer which electrically conducts the drain region and the buried layer and a drift region formed between the drain region and the channel region, which has the same conductive type as that of the drain region and has impurity concentration less than that of the drain region.
摘要翻译：半导体器件具有源极区，沟道区和漏极区，沿着衬底的表面依次形成，垂直型双极晶体管由衬底下面的源极区形成，垂直型双极晶体管的基极接触区，连接到垂直型双极晶体管的掩埋层，导电漏极区和掩埋层的掩埋接触层和形成在漏极区和沟道区之间的漂移区，其具有与漏极相同的导电类型并且杂质浓度小于漏极区的杂质浓度。

10. 发明申请

US20080251838A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080251838A1
公开(公告)日：2008-10-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
摘要翻译：半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上，以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式