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71. 发明授权

US09582201B2 Multi-tier scheme for logical storage management 有权
标题翻译：用于逻辑存储管理的多层方案
公开(公告)号：US09582201B2
公开(公告)日：2017-02-28
申请号：US14498566
申请日：2014-09-26
申请人： HGST Netherlands B.V.
发明人： Haining Liu , Yuriy Pavlenko , George G. Artnak, Jr.
IPC分类号： G11C8/02 , G06F3/06 , G11C8/12 , G11C5/02
CPC分类号： G06F3/0613 , G06F3/0635 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G11C5/025 , G11C5/14 , G11C8/12 , G11C29/021 , G11C29/028 , G11C2029/2602
摘要： A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
摘要翻译：存储设备可以包括控制器和包括布置在多个通道中的多个管芯的存储器阵列。在一些示例中，控制器可以被配置为基于与多个管芯相关联的相应的芯片使能线从存储器阵列定义多个管芯组，其中多个管芯组的每个管芯组包括在从所述多个通道中的每个通道至少一个管芯; 从所述多个模组的所选模组中定义多个块集，其中每个块集合包括来自所选芯片组的每个管芯的块; 接收要存储的数据单元; 并且发出导致数据单元被存储在多个块集合的所选块集的块中的命令。

72. 发明申请

US20170053678A1 ADHESIVE COVER SEAL FOR HERMETICALLY-SEALED DATA STORAGE DEVICE 审中-公开
标题翻译：用于密封数据存储设备的胶粘剂密封件
公开(公告)号：US20170053678A1
公开(公告)日：2017-02-23
申请号：US15168766
申请日：2016-05-31
申请人： HGST Netherlands B.V.
发明人： THOMAS R. ALBRECHT , DARYA AMIN-SHAHIDI , TOSHIKI HIRANO , KIRK B. PRICE
IPC分类号： G11B33/14
CPC分类号： G11B33/1466 , G11B25/043 , G11B33/022 , G11B33/027 , G11B33/1446 , G11B33/148 , G11B33/1486
摘要： A data storage device involves a plurality of sidewalls of a bent sheet metal cover, either pre-formed or shaped-in-place, overlapping with and hermetically sealed with a corresponding plurality of sidewalls of an enclosure base, using an applied epoxy adhesive or a pressure-sensitive adhesive tape seal. Base protrusions and/or cover dimples may be used to set a suitable gap between the parts. A robust hermetic seal provides for filling the data storage device with a lighter-than-air gas.
摘要翻译：数据存储装置包括弯曲的金属板的多个侧壁，其预成形或成形就位，与外壳基座的对应的多个侧壁重叠并且密封地密封，使用施加的环氧粘合剂或压敏胶带密封。基部突起和/或覆盖凹坑可用于在部件之间设置合适的间隙。强大的气密密封提供了使用轻于空气的气体来填充数据存储设备。

73. 发明申请

US20170053668A1 METHOD FOR MAKING A PERPENDICULAR MAGNETIC RECORDING WRITE HEAD WITH WRITE POLE HAVING THIN SIDE GAPS AND THICKER LEADING GAP 有权
标题翻译：用于制作具有薄边和厚度导线缝隙的写入磁头的全磁性记录写头的方法
公开(公告)号：US20170053668A1
公开(公告)日：2017-02-23
申请号：US14827705
申请日：2015-08-17
申请人： HGST Netherlands B.V.
发明人： April D. Hixson-Goldsmith , Ning Shi , Kyusik Shin , Suping Song , Brian R. York
IPC分类号： G11B5/31 , G11B5/127
CPC分类号： G11B5/3163 , G11B5/1278 , G11B5/232 , G11B5/3116 , G11B5/315
摘要： Ionized physical vapor deposition (IPVD) is used to form a magnetic recording disk drive write head main pole with thin side gap layers and a thicker leading gap layer. A metal or metal alloy is formed by IPVD in a trench with a bottom and outwardly sloping sidewalls. An optional Ru seed layer is deposited on the metal or metal alloy. This is followed by atomic layer deposition (ALD) of a Ru smoothing layer. If the IPVD results in metal or metal alloy side gap layers with a rough surface, the ALD process is modified, resulting in a smooth Ru smoothing layer that does not replicate the rough surface of the side gap layers.
摘要翻译：电离物理气相沉积（IPVD）用于形成磁记录盘驱动写头主极，具有薄侧间隙层和较厚的前导间隙层。通过IPVD在具有底部和向外倾斜侧壁的沟槽中形成金属或金属合金。可选的Ru籽晶层沉积在金属或金属合金上。这之后是Ru平滑层的原子层沉积（ALD）。如果IPVD导致具有粗糙表面的金属或金属合金侧间隙层，则ALD工艺被改变，导致不平滑侧面间隙层的粗糙表面的光滑的Ru平滑层。

74. 发明申请

US20170047114A1 CORRELATING PHYSICAL PAGE ADDRESSES FOR SOFT DECISION DECODING 有权
标题翻译：用于软决策解码的相关页面地址
公开(公告)号：US20170047114A1
公开(公告)日：2017-02-16
申请号：US14823751
申请日：2015-08-11
申请人： HGST Netherlands B.V.
发明人： Seung-Hwan Song , Kiran K. Gunnam , Zvonimir Z. Bandic
IPC分类号： G11C11/56 , G11C16/34 , G11C16/08 , G11C16/28
CPC分类号： G11C11/5642 , G11C16/08 , G11C16/28 , G11C16/3436 , G11C29/52
摘要： A storage device may include a processor and a memory device including a multilevel memory cell. The processor may correlate a first physical page address and a second physical page address, each address being associated with the multilevel memory cell. The processor also may apply a first read operation to the memory cell to determine a value of a first bit associated with the first physical page address. The processor additionally may apply at least a second read operation to the multilevel memory cell to determine a value of a second bit associated with the second physical page address. The processor may determine, based at least in part on the value of the first bit and the value of the second bit, a soft decision value associated with the second bit. The processor may verify the value of the second bit based at least in part on the soft decision value.
摘要翻译：存储设备可以包括处理器和包括多级存储器单元的存储器件。处理器可以将第一物理页地址和第二物理页地址相关联，每个地址与多层存储器单元相关联。处理器还可以向存储器单元应用第一读取操作以确定与第一物理页地址相关联的第一位的值。处理器还可以向多层存储器单元施加至少第二读取操作，以确定与第二物理页地址相关联的第二位的值。处理器可以至少部分地基于第一位的值和第二位的值来确定与第二位相关联的软判决值。至少部分地基于软判决值，处理器可以验证第二位的值。

75. 发明授权

US09558814B2 Hybrid analog and digital memory device 有权
标题翻译：混合模拟和数字存储设备
公开(公告)号：US09558814B2
公开(公告)日：2017-01-31
申请号：US14683850
申请日：2015-04-10
申请人： HGST Netherlands B.V.
发明人： Roger F. Galinggana, Jr. , James Arnold V. Gregana , Lloyd Henry I. Li
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5642 , G11C7/16 , G11C11/5628 , G11C16/0408 , G11C27/005
摘要： A memory cell including a floating gate transistor including a floating gate, and an analog sensor element adjacent to the floating gate, where an electrical characteristic of the analog sensor element is affected by an amount of charge on the floating gate.
摘要翻译：一种存储单元，包括一个包括浮动栅极的浮动栅极晶体管和一个与浮动栅极相邻的模拟传感器元件，模拟传感器元件的电气特性受到浮动栅极上的电荷量的影响。

76. 发明申请

US20170025476A1 ELECTROPLATED PHASE CHANGE SWITCH 审中-公开
公开(公告)号：US20170025476A1
公开(公告)日：2017-01-26
申请号：US15285610
申请日：2016-10-05
申请人： HGST Netherlands B.V.
发明人： Christian R. Bonhôte , Jeffrey LILLE
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L45/16 , H01L27/24 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/1608
摘要： The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.

77. 发明授权

US09552837B2 Vertically and horizontally weakly coupled perpendicular small grain media 有权
标题翻译：垂直和水平弱耦合的垂直小颗粒介质
公开(公告)号：US09552837B2
公开(公告)日：2017-01-24
申请号：US14070408
申请日：2013-11-01
申请人： HGST Netherlands B.V.
发明人： Hoa V. Do , Sylvia H. Florez , Yoshihiro Ikeda , Kentaro Takano , Bruce D. Terris , Qing Zhu
IPC分类号： G11B5/66
CPC分类号： G11B5/66
摘要： In one general embodiment, a magnetic medium includes a recording layer having at least three exchange control layers each having a magnetic moment less than 100 emu/cc, and four magnetic layers separated from one another by the exchange control layers. An uppermost of the magnetic layers is doped with oxygen. In another general embodiment, a magnetic medium includes a recording layer having at least three exchange control layers and four magnetic layers separated from one another by the exchange control layers. An uppermost of the magnetic layers has an oxygen content of greater than 0.5 vol %. An average pitch of magnetic grains in a lowermost of the magnetic layers is 9 nm or less. A lowermost of the magnetic layers has an oxide content of at least 20 vol %.
摘要翻译：在一个一般实施例中，磁介质包括具有至少三个具有小于100emu / cc的磁矩的交换控制层的记录层，以及由交换控制层彼此分开的四个磁性层。最上面的磁性层被氧掺杂。在另一个一般实施例中，磁介质包括具有至少三个交换控制层的记录层和由交换控制层彼此分开的四个磁性层。最上面的磁性层的氧含量大于0.5体积％。最下面的磁性层的磁性粒子的平均间距为9nm以下。最下层的磁性层的氧化物含量至少为20体积％。

78. 发明申请

US20170018707A1 METHOD FOR FABRICATING MRAM BITS ON A TIGHT PITCH 有权
标题翻译：一种用于在紧凑的座位上制造MRAM位置的方法
公开(公告)号：US20170018707A1
公开(公告)日：2017-01-19
申请号：US15280094
申请日：2016-09-29
申请人： HGST Netherlands B.V.
发明人： Jordan A. KATINE
IPC分类号： H01L43/12 , H01L27/22
CPC分类号： H01L43/12 , H01L27/222 , H01L43/02 , H01L43/10
摘要： A method for fabricating magnetoresistive random access memory (MRAM) devices on a tight pitch is provided. The method generally includes etching a pattern of columns into a hardmask layer disposed on a magnetic tunnel junction (MTJ) disposed on a substrate having electrically conductive contacts, the MTJ comprising a tunnel barrier layer between first and second ferromagnetic layers, the pattern of columns aligned to the electrically conductive contacts; etching the first ferromagnetic layer to expose the tunnel barrier layer and to form columns comprising the hardmask layer and the first ferromagnetic layer; forming a passivation layer on the exposed tunnel barrier layer and on top side surfaces of the columns; and etching the passivation layer on the exposed tunnel barrier layer, the exposed tunnel barrier layer, and the second ferromagnetic layer to form columns comprising the hardmask layer, the first ferromagnetic layer, the tunnel barrier layer, and the second ferromagnetic layer.
摘要翻译：提供了一种用于制造紧密间距的磁阻随机存取存储器（MRAM）器件的方法。该方法通常包括将列的图案蚀刻到设置在具有导电触点的衬底上的磁性隧道结（MTJ）上的硬掩模层中，MTJ包括在第一和第二铁磁层之间的隧道势垒层，到导电触点; 蚀刻第一铁磁层以暴露隧道势垒层并形成包括硬掩模层和第一铁磁层的柱; 在暴露的隧道势垒层和柱的顶侧表面上形成钝化层; 以及蚀刻暴露的隧道势垒层，暴露的隧道势垒层和第二铁磁层上的钝化层，以形成包括硬掩模层，第一铁磁层，隧道势垒层和第二铁磁层的列。

79. 发明申请

US20170018283A1 METHOD TO COAT NFT AREA WITH HIGHLY THERMAL CONDUCTING MATERIAL IN HAMR STRUCTURE 有权
标题翻译：在HAMR结构中涂覆高导热材料的NFT区域的方法
公开(公告)号：US20170018283A1
公开(公告)日：2017-01-19
申请号：US15280071
申请日：2016-09-29
申请人： HGST Netherlands B.V.
发明人： Eduardo TORRES , Cherngye HWANG , Randy SIMMONS
IPC分类号： G11B5/31 , G11B5/40
CPC分类号： G11B5/3163 , G11B5/3133 , G11B5/314 , G11B5/40 , G11B2005/0021
摘要： Embodiments disclosed herein generally relate to a method for forming a HAMR head. The method includes depositing a drop-on-demand mask on a portion of a surface of a slider using a drop-on-demand tool. The surface of the slider includes at least a portion of an NFT. A first protective layer is deposited over a remaining portion of the surface of the slider and over the drop-on-demand mask. The drop-on-demand mask and a portion of the first protective layer disposed on the drop-on-demand mask are removed, exposing at least the portion of the NFT. A second protective layer is deposited on the first protective layer and at least the exposed portion of the NFT. By using the drop-on-demand tool to deposit the drop-on-demand mask, the alignment between the drop-on-demand mask and the portion of the NFT is less stringent, and the drop-on-demand mask can be easily removed using a wiping tool.
摘要翻译：本文公开的实施例通常涉及用于形成HAMR头的方法。该方法包括使用按需点滴工具在滑块的表面的一部分上放置按需点阵的掩模。滑块的表面包括NFT的至少一部分。第一保护层沉积在滑块的表面的剩余部分上并且在按需滴下的掩模上。去除了按需涂色面罩和设置在按需滴下面膜上的第一保护层的一部分，至少露出NFT的一部分。第二保护层沉积在NFT的第一保护层和至少暴露的部分上。通过使用按需点滴工具来存储按需点亮的掩模，按需点阵掩码与NFT部分之间的对准不太严格，并且按需点亮的掩码可以很容易使用擦拭工具取出。

80. 发明申请

US20170017578A1 GENERATION OF RANDOM ADDRESS MAPPING IN NON-VOLATILE MEMORIES USING LOCAL AND GLOBAL INTERLEAVING 有权
标题翻译：使用本地和全球交互的非易失性存储器中随机地址映射的生成
公开(公告)号：US20170017578A1
公开(公告)日：2017-01-19
申请号：US14967169
申请日：2015-12-11
申请人： HGST Netherlands B.V.
发明人： Kiran Kumar Gunnam
IPC分类号： G06F12/10
CPC分类号： G06F12/1072 , G06F8/458 , G06F9/52 , G06F12/02 , G06F12/0246 , G06F12/0607 , G06F2201/825 , G06F2212/154 , G06F2212/202 , G06F2212/608 , G06F2212/7201 , G06F2212/7211
摘要： Systems and methods for generating random address mapping in non-volatile memories using local and global interleaving are provided. One such method for generating a random address mapping for a non-volatile memory (NVM) involves identifying a number of bits (N) in a physical address space of the NVM, selecting G bit(s) of the N bits to be used for global interleaving, where G is less than N, determining a number of bits (N-G) to be used for local interleaving, mapping the G bit(s) using a mapping function for global interleaving, interleaving (N-G) bits using an interleaving function for local interleaving, and generating a combined mapping comprising the mapped G bit(s) and the interleaved (N-G) bits.
摘要翻译：提供了使用局部和全局交错在非易失性存储器中产生随机地址映射的系统和方法。用于产生用于非易失性存储器（NVM）的随机地址映射的一种这样的方法涉及识别NVM的物理地址空间中的位数（N），选择要用于的N位的G位全局交错，其中G小于N，确定要用于本地交织的比特数（NG），使用用于全局交织的映射函数映射G比特，使用交织功能交织（NG）比特，并且生成包括映射的G位和交错（NG）位的组合映射。

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