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71. 发明授权

US08754503B2 Substrate strip plate structure for semiconductor device and method for manufacturing the same 失效
标题翻译：用于半导体器件的基板带状板结构及其制造方法
公开(公告)号：US08754503B2
公开(公告)日：2014-06-17
申请号：US13355946
申请日：2012-01-23
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/1218
摘要： The present invention provides a strip plate structure and a method for manufacturing the same. The strip plate structure comprises a strip plate array, which comprises a plurality of strip plates arranged with spacing in a predetermined direction on a same plane, wherein each of the strip plates has a first surface and a second surface opposite to the first surface and the strip plate array is arranged on a plane parallel to the first surface of the strip plates; a plurality of strip sheets which connect neighboring ones of the strip plates; flexible material layers, which are located on at least a portion of the surfaces of the strip sheets and/or on at least a portion of the surfaces of the strip plates.
摘要翻译：本发明提供一种带状板结构及其制造方法。带状板结构包括条板阵列，其包括在同一平面上以预定方向间隔布置的多个带状板，其中每个带状板具有第一表面和与第一表面相对的第二表面，带板阵列布置在平行于带状板的第一表面的平面上; 多个带状片，其连接相邻的条板; 柔性材料层位于带状片的至少一部分表面上和/或在带状板的至少一部分表面上。

72. 发明授权

US08674449B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08674449B2
公开(公告)日：2014-03-18
申请号：US13576550
申请日：2011-11-25
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/70 , H01L27/088
CPC分类号： H01L29/785 , H01L27/0924 , H01L29/66795
摘要： A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.
摘要翻译：公开了一种半导体器件及其制造方法。在一个实施例中，半导体器件可以包括半导体层，通过图案化半导体层形成的鳍和跨在翅片上的栅极堆叠。鳍可以在其底部包括掺杂块区域。根据本实施方式，能够通过块区域有效地抑制翅片底部的电流泄漏。

73. 发明授权

US08643061B2 Structure of high-K metal gate semiconductor transistor 有权
标题翻译：高K金属栅半导体晶体管的结构
公开(公告)号：US08643061B2
公开(公告)日：2014-02-04
申请号：US12908024
申请日：2010-10-20
申请人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
发明人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
IPC分类号： H01L29/66
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
摘要翻译：提供半导体结构。该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是通过一层硅 - 锗（SiGe）。应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。还提供了形成半导体结构的方法。

74. 发明授权

US08637935B2 Semiconductor device including embedded isolation regions and method for forming the same 有权
标题翻译：包括嵌入式隔离区的半导体器件及其形成方法
公开(公告)号：US08637935B2
公开(公告)日：2014-01-28
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

75. 发明授权

US08598666B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08598666B2
公开(公告)日：2013-12-03
申请号：US13504935
申请日：2011-11-03
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L21/743 , H01L27/1218 , H01L29/78
摘要： The present invention relates to a semiconductor structure and a method for manufacturing the same. A semiconductor structure comprises: a semiconductor substrate; a first insulating material layer, a first conductive material layer, a second insulating material layer, a second conductive material layer and an insulating buried layer formed in sequence on the semiconductor substrate; a semiconductor layer bonded on the insulating buried layer; transistors formed on the semiconductor layer, the channel regions of the transistors each being formed in the semiconductor layer and each having a back-gate formed from the second conductive material layer; a dielectric layer covering the semiconductor layer and the transistors; isolation structures for at least electrically isolating each transistor from its adjacent transistors, the top of the isolation structures being flush with or slightly higher than the upper surface of the semiconductor layer, and the bottom of the isolation structures being in the second insulating material layer; and a conductive contact running through the dielectric layer and extending down into the first conductive material layer.
摘要翻译：半导体结构及其制造方法技术领域本发明涉及半导体结构及其制造方法。半导体结构包括：半导体衬底; 在半导体衬底上依次形成第一绝缘材料层，第一导电材料层，第二绝缘材料层，第二导电材料层和绝缘掩埋层; 接合在绝缘掩埋层上的半导体层; 形成在半导体层上的晶体管，晶体管的沟道区各自形成在半导体层中，每一个具有由第二导电材料层形成的背栅; 覆盖半导体层和晶体管的电介质层; 用于至少将每个晶体管与其相邻晶体管电隔离的隔离结构，隔离结构的顶部与半导体层的上表面齐平或略高，隔离结构的底部位于第二绝缘材料层中; 以及导电接触件，其穿过介电层并向下延伸到第一导电材料层中。

76. 发明授权

US08557652B2 Application of cluster beam implantation for fabricating threshold voltage adjusted FETs 失效
公开(公告)号：US08557652B2
公开(公告)日：2013-10-15
申请号：US13608422
申请日：2012-09-10
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

77. 发明申请

US20130256845A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20130256845A1
公开(公告)日：2013-10-03
申请号：US13512330
申请日：2012-04-09
申请人： Haizhou Yin , Wei Jiang
发明人： Haizhou Yin , Wei Jiang
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232 , H01L29/7833
摘要： The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability.
摘要翻译：本发明公开了一种半导体器件，其包括：衬底和衬底中的浅沟槽隔离，其特征在于，所述半导体器件还包括在所述衬底和所述浅沟槽隔离之间的应力释放层。在根据本发明的半导体器件及其制造方法中，通过在衬底和STI之间插入由较软材料制成的应力释放层，可以释放在形成STI期间累积的应力，从而减少器件基板的漏电流，提高器件的可靠性。

78. 发明申请

US20130256810A1 Semiconductor Device and Method for Manufacturing the Same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20130256810A1
公开(公告)日：2013-10-03
申请号：US13512329
申请日：2012-04-09
申请人： Haizhou Yin , Wei Jiang
发明人： Haizhou Yin , Wei Jiang
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L21/76232 , H01L29/0638 , H01L29/7833
摘要： The present invention discloses a semiconductor device, which comprises: a first epitaxial layer on a substrate; a second epitaxial layer on the first epitaxial layer, wherein a MOSFET is formed in an active region of the second epitaxial layer; and an inverted-T shaped STI formed in the first epitaxial layer and the second epitaxial layer and surrounding the active region. In the semiconductor device and the method for manufacturing the same according to the present invention, the double epitaxial layers are selectively etched to form an inverted-T shaped STI, which effectively reduces the leakage current of the device without reducing the area of the active region, thereby improving the device reliability.
摘要翻译：本发明公开了一种半导体器件，其包括：衬底上的第一外延层; 在所述第一外延层上的第二外延层，其中在所述第二外延层的有源区中形成MOSFET; 以及形成在第一外延层和第二外延层中并围绕有源区的倒T形STI。在根据本发明的半导体器件及其制造方法中，选择性地蚀刻双重外延层以形成倒T形STI，其有效地减少器件的漏电流而不减少有源区的面积，从而提高了设备的可靠性。

79. 发明授权

US08546910B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08546910B2
公开(公告)日：2013-10-01
申请号：US13380723
申请日：2011-08-24
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/70
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78696
摘要： The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions. Accordingly, the present invention further provides a method for manufacturing a semiconductor structure, which is favorable for reducing the contact resistance at the source/drain regions, enhancing the device performance, lowering the cost and simplifying the manufacturing process.
摘要翻译：本发明提供一种半导体结构，其包括衬底，半导体基底，空腔，栅极堆叠，侧壁间隔物，源极/漏极区域和接触层; 其中，所述栅极堆叠位于所述半导体基底上，所述侧壁间隔物位于所述栅极堆叠的侧壁上，所述源极/漏极区域被嵌入所述半导体基底内并且位于所述栅极堆叠的两侧，所述腔体嵌入衬底和半导体衬底悬挂在空腔上，半导体衬底的中间部分的厚度大于沿着栅极长度方向的半导体衬底的两端的厚度，并且半导体衬底的两端沿着所述栅极宽度的方向与所述基板连接; 接触层覆盖源极/漏极区域的暴露表面。因此，本发明还提供了一种制造半导体结构的方法，其有利于降低源/漏区的接触电阻，提高器件性能，降低成本并简化制造工艺。

80. 发明授权

US08497197B2 Method for manufacturing a high-performance semiconductor structure with a replacement gate process and a stress memorization technique 有权
标题翻译：用替代栅极工艺和应力记忆技术制造高性能半导体结构的方法
公开(公告)号：US08497197B2
公开(公告)日：2013-07-30
申请号：US13061296
申请日：2010-09-26
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/26586 , H01L29/1083 , H01L29/51 , H01L29/66575 , H01L29/7833 , H01L29/7847
摘要： A method for manufacturing a semiconductor structure includes providing an n-type field effect transistor comprising a source region, a drain region, and a first gate; forming a tensile stress layer on the n-type field effect transistor; removing the first gate so as to form a gate opening; performing an anneal so that the source region and the drain region memorize a stress induced by the tensile stress layer; forming a second gate; removing the tensile stress layer; and forming an interlayer dielectric layer on the n-type field effect transistor. A replacement process is combined with a stress memorization technique for enhancing the stress memorization effect and increasing mobility of electrons, which in turn improves overall properties of the semiconductor structure.
摘要翻译：一种制造半导体结构的方法，包括提供包括源区，漏区和第一栅极的n型场效应晶体管; 在n型场效应晶体管上形成拉伸应力层; 移除第一门以形成门开口; 进行退火，使得源极区域和漏极区域记忆由拉伸应力层引起的应力; 形成第二个门; 去除拉应力层; 以及在n型场效应晶体管上形成层间电介质层。替代过程与用于增强应力记忆效应和增加电子迁移率的应力记忆技术相结合，这又改善了半导体结构的整体性能。

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