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71. 发明授权

US06567968B1 Block level routing architecture in a field programmable gate array 失效
标题翻译：块级路由架构在现场可编程门阵列中
公开(公告)号：US06567968B1
公开(公告)日：2003-05-20
申请号：US09519081
申请日：2000-03-06
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： G06F1750
CPC分类号： H03K19/17736 , H01L27/11803
摘要： An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Block (EB) 3×3 switch matrix. A second side of each EB 3×3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3×3 switch matrix may be coupled to the leads on the second side of second EB3×3 switch matrix by BC criss-cross extension.
摘要翻译： FPGA架构具有顶级，中级和低级。该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。中层层次的B16x16瓦片是16块16块阵列。中间层次的路由资源是包括互连导体组的高速公路路由信道M1，M2和M3。在半层次FPGA架构的最底层，有块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导线。每个BC路由信道被耦合到高速公路标签，以分别向高速公路路由信道M1，M2和M3提供每个B1块的接入。每个BC路由信道具有九个互连导体，它们分成三组三个互连导体。每组三个互连导体连接到扩展块（EB）3x3开关矩阵的第一侧。每个EB 3x3开关矩阵的第二面耦合到E-tab。在相邻B1块之间，在水平和垂直方向上，第一EB 3×3开关矩阵的第二侧上的引线可以通过BC交叉扩展耦合到第二EB3×3开关矩阵的第二侧上的引线。

72. 发明授权

US06285212B1 Block connector splitting in logic block of a field programmable gate array 有权
标题翻译：在现场可编程门阵列的逻辑块中的块连接器分离
公开(公告)号：US06285212B1
公开(公告)日：2001-09-04
申请号：US09518973
申请日：2000-03-06
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： A03K19177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Within the B1 block, a horizontal BC routing channel is disposed between two upper and two lower clusters of devices, and a vertical BC routing channel is disposed between two clusters of devices on the left side of the B1 block and two clusters of devices on the right side of the B1 block. The BC routing channel forms intersections with the inputs and outputs of the devices in the clusters. The horizontal BC routing channel forms a first diagonally hardwired connection with a routing channel that effectively sends the horizontal BC routing channel in a vertical direction. A second diagonally hardwired connection pairwise shorts the horizontal and vertical BC routing channels to provide dual accessibility to the logic resources in the B1 block from more than one side. Disposed between the first diagonally hardwired connection and the second diagonally hardwired connection is a BC splitting extension which provides a programmable one-to-one coupling between the interconnect conductors of the horizontal BC routing channel on either side of the BC splitting extension.
摘要翻译： FPGA架构具有顶级，中级和低级。该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。中层层次的B16x16瓦片是16块16块阵列。中间层次的路由资源是包括互连导体组的高速公路路由信道M1，M2和M3。在半层次FPGA架构的最底层，存在块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导体，以将逻辑元件连接到更多的路由资源。在B1块内，水平BC路由信道被布置在两个上和下两个设备群集之间，并且垂直BC路由信道被布置在B1块的左侧的两个设备群集之间，并且两个设备群集 B1区右侧。 BC路由信道与集群中的设备的输入和输出形成交集。水平BC路由信道与路由信道形成第一对角线硬连线，路由信道在垂直方向上有效地发送水平BC路由信道。第二个对角线硬连线成对地缩短了水平和垂直BC路由信道，从而提供了来自不同一侧的B1块中的逻辑资源的双重可访问性。设置在第一对角线硬连线连接和第二对角线硬连线连接之间的是BC分割扩展，其在BC分割扩展的任一侧上的水平BC路由信道的互连导体之间提供可编程的一对一耦合。

73. 发明授权

US5744980A Flexible, high-performance static RAM architecture for field-programmable gate arrays 失效
标题翻译：用于现场可编程门阵列的灵活高性能静态RAM架构
公开(公告)号：US5744980A
公开(公告)日：1998-04-28
申请号：US603597
申请日：1996-02-16
申请人： John E. McGowan , William C. Plants , Joel D. Landry , Sinan Kaptanoglu , Warren K. Miller
发明人： John E. McGowan , William C. Plants , Joel D. Landry , Sinan Kaptanoglu , Warren K. Miller
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17704
摘要： A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof. Each of the random access memory blocks has address inputs, control inputs, data inputs, and data outputs. User-programmable interconnect elements are connected between the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks and selected ones of the interconnect conductors in the horizontal routing channels passing therethrough. Programming circuitry is provided for programming selected ones of the user-programmable interconnect conductors to connect the inputs and outputs of the logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks.
摘要翻译：现场可编程门阵列架构包括多个水平和垂直路由通道，每个路由通道包括多个互连导体。一些互连导体由用户可编程互连元件分段，并且一些水平和垂直互连导体可由位于它们之间的选定交叉处的用户可编程互连元件连接。每个具有至少一个输入和一个输出的逻辑功能模块的行和列阵列叠加在路由信道上。逻辑功能模块的输入和输出可连接到水平和垂直路由通道中的一个或两者中的互连导体中的一个。至少一列随机存取存储器块被布置在阵列中。每个随机存取存储器块跨越阵列的多于一行的距离，使得多于一个的水平路由信道通过其中并且可连接到其任一侧的相邻逻辑功能模块。每个随机存取存储块具有地址输入，控制输入，数据输入和数据输出。用户可编程互连元件连接在随机存取存储器块的地址输入，控制输入，数据输入和数据输出以及通过其中的水平路由通道中的选定的互连导体。提供了编程电路，用于编程用户可编程互连导体中的所选择的一个以将逻辑功能模块的输入和输出彼此连接，并将随机存取存储器块的地址输入，控制输入，数据输入和数据输出。

74. 发明授权

US5606267A Programmable logic module and architecture for field programmable gate array device 失效
公开(公告)号：US5606267A
公开(公告)日：1997-02-25
申请号：US522945
申请日：1995-09-01
申请人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
发明人： Khaled A. El Ayat , Gregory W. Bakker , Jung-Cheun Lien , William C. Plants , Sinan Kaptanoglu , Runip Gopisetty , King W. Chan , Marko Chew
IPC分类号： H03K19/177 , G01R31/28 , G01R31/3185 , H03K19/173
CPC分类号： G01R31/2884 , G01R31/318519 , H03K19/17704 , H03K19/17728
摘要： A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

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