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71. 发明授权

US07421564B1 Incrementing successive write operations to a plurality of memory devices 有权
标题翻译：将连续的写入操作递增到多个存储器件
公开(公告)号：US07421564B1
公开(公告)日：2008-09-02
申请号：US11356150
申请日：2006-02-17
申请人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
发明人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
IPC分类号： G06F12/06
CPC分类号： G06F12/0684 , G06F12/02 , G06F12/0813
摘要： A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a given address range. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
摘要翻译：集中式存储器分配系统利用写指针漂移校正。内存存储数据单元。存储器控制器接收与数据单元相关联的写请求，并将数据单元存储在存储器中。存储器控制器还发送包括存储数据单元的地址的应答。控制逻辑接收答复，并确定答复中的地址是否与给定地址范围与其他存储器控制器相关的回复中包含的地址不同。当这种情况发生时，控制逻辑执行纠正措施以使与存储器控制器相关联的地址返回到定义的范围内。

72. 发明授权

US07359321B1 Systems and methods for selectively performing explicit congestion notification 有权
标题翻译：选择性地执行显式拥塞通知的系统和方法
公开(公告)号：US07359321B1
公开(公告)日：2008-04-15
申请号：US10206990
申请日：2002-07-30
申请人： Pradeep Sindhu , Debashis Basu , Jayabharat Boddu , Avanindra Godbole
发明人： Pradeep Sindhu , Debashis Basu , Jayabharat Boddu , Avanindra Godbole
IPC分类号： G01R31/08
CPC分类号： H04L47/12 , H04L47/10 , H04L47/11 , H04L47/29 , H04L47/30 , H04L47/32 , H04L47/35
摘要： A system provides congestion control and includes multiple queues that temporarily store data and a drop engine. The system associates a value with each of the queues, where each of the values relates to an amount of memory associated with the queue. The drop engine compares the value associated with a particular one of the queues to one or more programmable thresholds and selectively performs explicit congestion notification or packet dropping on data in the particular queue based on a result of the comparison.
摘要翻译：系统提供拥塞控制，并且包括临时存储数据的多个队列和丢弃引擎。系统将值与每个队列相关联，其中每个值与与队列相关联的内存量相关。丢包引擎将与特定队列相关联的值与一个或多个可编程阈值进行比较，并且基于比较的结果选择性地对特定队列中的数据进行显式拥塞通知或分组丢弃。

73. 发明授权

US07289503B1 Systems and methods for efficient multicast handling 有权
标题翻译：用于高效多播处理的系统和方法
公开(公告)号：US07289503B1
公开(公告)日：2007-10-30
申请号：US10206999
申请日：2002-07-30
申请人： Pradeep Sindhu , Debashis Basu , Pankaj Patel , Raymond Lim , Avanindra Godbole , Tatao Chuang , Chi-Chung K. Chen , Jeffrey G. Libby , Dennis Ferguson , Philippe Lacroute , Gerald Cheung
发明人： Pradeep Sindhu , Debashis Basu , Pankaj Patel , Raymond Lim , Avanindra Godbole , Tatao Chuang , Chi-Chung K. Chen , Jeffrey G. Libby , Dennis Ferguson , Philippe Lacroute , Gerald Cheung
IPC分类号： H04L12/28
CPC分类号： H04L12/4633 , H04L12/66
摘要： A network device includes an interface and packet processing logic. The interface receives a multicast packet. The packet processing logic determines identifier data corresponding to the received multicast packet and replicates the identifier data to multiple outgoing packet forward engines at a first point in a processing path. The packet processing logic further replicates the identifier data to multiple data streams at a second point in the processing path and replicates the identifier data to multiple logical interfaces in the same stream at a third point in the processing path.
摘要翻译：网络设备包括接口和分组处理逻辑。接口收到组播报文。分组处理逻辑确定与所接收的多播分组相对应的标识符数据，并且在处理路径的第一点将标识符数据复制到多个输出分组转发引擎。分组处理逻辑还将标识符数据复制到处理路径中的第二点处的多个数据流，并且在处理路径中的第三点将标识符数据复制到同一流中的多个逻辑接口。

74. 发明授权

US07039774B1 Memory allocation using a memory address pool 失效
标题翻译：使用内存地址池进行内存分配
公开(公告)号：US07039774B1
公开(公告)日：2006-05-02
申请号：US10062424
申请日：2002-02-05
申请人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
发明人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
IPC分类号： G06F12/00
CPC分类号： G06F12/023
摘要： A system for managing memory includes a memory and a memory allocation unit. The memory stores a pool of memory addresses for writing data to the memory and stores a counter value. The memory allocation unit retrieves memory addresses from the pool in response to write requests from data sources. The memory allocation unit further replenishes the memory addresses in the pool when the pool is emptied and increments the counter value in response to each replenishment of the memory addresses in the pool.
摘要翻译：用于管理存储器的系统包括存储器和存储器分配单元。存储器存储用于将数据写入存储器的存储器地址池并存储计数器值。内存分配单元响应于来自数据源的写入请求从池中检索存储器地址。当池被清空时，存储器分配单元进一步补充池中的存储器地址，并响应于池中的存储器地址的每次补充递增计数器值。

75. 发明授权

US09331929B1 Methods and apparatus for randomly distributing traffic in a multi-path switch fabric 有权
标题翻译：在多路径交换矩阵中随机分配流量的方法和装置
公开(公告)号：US09331929B1
公开(公告)日：2016-05-03
申请号：US13433960
申请日：2012-03-29
申请人： Philip A. Thomas , Sarin Thomas , Jean-Marc Frailong , Pradeep Sindhu
发明人： Philip A. Thomas , Sarin Thomas , Jean-Marc Frailong , Pradeep Sindhu
IPC分类号： H04J3/06 , H04L12/26 , H04L12/755
CPC分类号： H04L43/50 , H04L43/0817 , H04L43/16 , H04L45/021 , H04L49/1515 , H04L49/1523
摘要： At a first time, a schedule module is configured to access a list of status indicators associated with a group of egress port indicators. The list of status indicators includes a set of status indicators each of which has a value greater than a threshold. The schedule module is configured to randomly select a status indicator from the set of status indicators and configured to reduce the value of the selected status indicator. The schedule module is then configured to send the egress port indicator associated with the selected status indicator such that a data cell is sent from an egress port associated with that egress port indicator. At a second time, when the value of every status indicator from the list of status indicators is not greater than the threshold, the schedule module is configured to increase the value of every status indicator above the threshold.
摘要翻译：在第一时间，调度模块被配置为访问与一组出口端口指示符相关联的状态指示符的列表。状态指示器的列表包括一组状态指示器，每个状态指示器的值大于阈值。调度模块被配置为从状态指示符集中随机选择状态指示符并且被配置为减少所选状态指示符的值。然后，调度模块被配置为发送与所选状态指示符相关联的出口端口指示符，使得从与该出口端口指示符相关联的出口端口发送数据信元。第二次，当状态指示器列表中的每个状态指示符的值不大于阈值时，调度模块被配置为将每个状态指示符的值增加到阈值以上。

76. 发明授权

US08964556B2 Methods and apparatus for flow-controllable multi-staged queues 有权
标题翻译：流量可控的多级队列的方法和装置
公开(公告)号：US08964556B2
公开(公告)日：2015-02-24
申请号：US13544604
申请日：2012-07-09
申请人： Avanindra Godbole , Pradeep Sindhu , Jean-Marc Frailong
发明人： Avanindra Godbole , Pradeep Sindhu , Jean-Marc Frailong
IPC分类号： H04L12/26 , H04L12/801 , H04L12/54 , H04L12/825 , H04L12/869 , H04L12/835 , H04L12/861 , H04L12/931
CPC分类号： H04L47/30 , H04L47/10 , H04L47/11 , H04L47/26 , H04L47/263 , H04L47/266 , H04L47/50 , H04L47/60 , H04L49/505 , H04L49/90
摘要： In one embodiment, a method includes sending a first flow control signal to a first stage of transmit queues when a receive queue is in a congestion state. The method also includes sending a second flow control signal to a second stage of transmit queues different from the first stage of transmit queues when the receive queue is in the congestion state.
摘要翻译：在一个实施例中，一种方法包括当接收队列处于拥塞状态时，向发射队列的第一级发送第一流控制信号。该方法还包括当接收队列处于拥塞状态时，将第二流控制信号发送到与发送队列的第一级不同的发送队列的第二级。

77. 发明授权

US08880808B1 Centralized memory allocation with write pointer drift correction 有权
标题翻译：集中存储器分配与写指针漂移校正
公开(公告)号：US08880808B1
公开(公告)日：2014-11-04
申请号：US12181930
申请日：2008-07-29
申请人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
发明人： Rami Rahim , Pradeep Sindhu , Raymond Marcelino Manese Lim , Sreeram Veeragandham , David Skinner
IPC分类号： G06F12/06 , G06F12/02
CPC分类号： G06F12/0684 , G06F12/02 , G06F12/0813
摘要： A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.
摘要翻译：用于写入数据的系统包括存储器，至少一个存储器控制器和控制逻辑。内存存储数据单元。存储器控制器接收与数据单元相关联的写请求，并将数据单元存储在存储器中。存储器控制器还发送包括存储数据单元的地址的应答。控制逻辑接收答复并确定答复中的地址是否与包含在与其他存储器控制器相关联的应答中的地址相差阈值。当这种情况发生时，控制逻辑执行纠正措施以使与存储器控制器相关联的地址返回到定义的范围内。

78. 发明授权

US08811163B2 Methods and apparatus for flow control associated with multi-staged queues 有权
标题翻译：与多级队列相关联的流控制的方法和装置
公开(公告)号：US08811163B2
公开(公告)日：2014-08-19
申请号：US13441083
申请日：2012-04-06
申请人： Avanindra Godbole , Pradeep Sindhu , Jean-Marc Frailong
发明人： Avanindra Godbole , Pradeep Sindhu , Jean-Marc Frailong
IPC分类号： H04L12/24 , H04L12/56
CPC分类号： H04L47/30 , H04L47/10 , H04L47/11 , H04L47/26 , H04L47/263 , H04L47/266 , H04L47/50 , H04L47/60 , H04L49/505 , H04L49/90
摘要： In one embodiment, a method, comprising receiving at a receive side of a physical link a request to suspend transmission of data from a queue within a transmit side of a first stage of queues and to suspend transmission via a path including the physical link, a portion of the first stage of queues, and a portion of a second stage of queues. The method includes sending, in response to the request, a flow control signal to a flow control module configured to schedule transmission of the data from the queue within the transmit side of the first stage of queues. The flow control signal is associated with a first control loop including the path and differing from a second control loop that excludes the first stage of queues.
摘要翻译：在一个实施例中，一种方法，包括在物理链路的接收侧接收暂停从队列的第一级的发送侧内的队列传输数据的请求，并且经由包括所述物理链路的路径暂停发送，队列的第一阶段的部分和队列的第二阶段的一部分。该方法包括响应于该请求向流控制模块发送流控制信号，该流控制模块被配置为调度在队列的第一级的发送侧内的队列的数据传输。流控制信号与包括路径的第一控制回路相关联，并且与排除第一级队列的第二控制循环不同。

79. 发明授权

US08804710B2 System architecture for a scalable and distributed multi-stage switch fabric 有权
标题翻译：用于可扩展和分布式多级交换结构的系统架构
公开(公告)号：US08804710B2
公开(公告)日：2014-08-12
申请号：US12345500
申请日：2008-12-29
申请人： Gunes Aybay , Jaya Bandyopadhyay , Jean-Marc Frailong , Pradeep Sindhu , Philip A. Thomas , Anjan Venkatramani
发明人： Gunes Aybay , Jaya Bandyopadhyay , Jean-Marc Frailong , Pradeep Sindhu , Philip A. Thomas , Anjan Venkatramani
IPC分类号： H04L12/50 , H04L12/56
CPC分类号： H04L49/40 , H04L49/00 , H04L49/1515
摘要： In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.
摘要翻译：在一些实施例中，装置包括第一壳体，第二壳体和至少一个电缆。第一壳体包括交换结构的第一接口卡。第二壳体包括交换结构的第二接口卡和交换结构的第三接口卡。交换结构的第二接口卡经由中间平面操作和物理地耦合到交换结构的第三接口卡。第二接口卡限定了与第三接口卡所定义的平面不平行的平面和由中平面限定的平面。由第三接口卡定义的平面与由第二接口卡定义的平面和由中平面限定的平面不平行。电缆被配置为将第一接口卡可操作地耦合到第二接口卡。

80. 发明授权

US08798074B1 Packet queueing within ring networks 有权
标题翻译：环网内的数据包排队
公开(公告)号：US08798074B1
公开(公告)日：2014-08-05
申请号：US13275059
申请日：2011-10-17
申请人： Kireeti Kompella , Pradeep Sindhu , Jean-Marc Frailong , David J. Ofelt
发明人： Kireeti Kompella , Pradeep Sindhu , Jean-Marc Frailong , David J. Ofelt
IPC分类号： H04L12/28 , H04L12/54 , H04L12/56
CPC分类号： H04L12/5693 , H04L12/437 , H04L47/10 , H04L47/50
摘要： In general, techniques are described for packet queuing within ring networks. In accordance with the techniques, a network device of a ring network comprises a memory having a different queue for each order-dependent pair of the network devices. Each pair represents a different order-dependent combination of the network devices that includes an ingress network device that provides an ingress to the ring network and an egress network device that provides an egress from the ring network. The network device further comprises an interface for receiving a packet from a neighboring one of the plurality of network devices and a control unit that, in response to receiving the packet, stores the packet to one of the queues based on which network devices is the ingress and which network device is the egress for the packet. The control unit forwards the stored packet via the ring network according to a scheduling algorithm.
摘要翻译：一般来说，技术描述为环形网络内的数据包排队。根据这些技术，环形网络的网络设备包括具有针对网络设备的每个顺序依赖对的不同队列的存储器。每对代表网络设备的不同顺序组合，其包括向环网提供入口的入口网络设备和从环网提供出口的出口网络设备。所述网络设备还包括用于从所述多个网络设备中的相邻的一个网络设备接收分组的接口和响应于接收到所述分组而将所述分组存储到所述队列中的一个基于哪个网络设备是所述入口的控制单元哪个网络设备是分组的出口。控制单元根据调度算法经由环网转发存储的分组。

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