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71. 发明授权

US06391210B2 Process for manufacturing a multi-layer circuit board 失效
标题翻译：制造多层电路板的工艺
公开(公告)号：US06391210B2
公开(公告)日：2002-05-21
申请号：US09901848
申请日：2001-07-09
申请人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
发明人： Bernd K. Appelt , John M. Lauffer , Voya R. Markovich , Irving Memis , David J. Russell
IPC分类号： H01B1300
CPC分类号： H05K3/4652 , H05K3/0023 , H05K3/0035 , H05K2203/0508 , H05K2203/0554
摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.
摘要翻译：一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。

72. 发明授权

US06281452B1 Multi-level thin-film electronic packaging structure and related method 失效
标题翻译：多层薄膜电子封装结构及相关方法
公开(公告)号：US06281452B1
公开(公告)日：2001-08-28
申请号：US09204851
申请日：1998-12-03
申请人： Chandrika Prasad , Roy Yu , Richard L. Canull , Giulio DiGiacomo , Ajay P. Giri , Lewis S. Goldmann , Kimberley A. Kelly , Bouwe W. Leenstra , Voya R. Markovich , Eric D. Perfecto , Sampath Purushothaman , Joseph M. Sullivan
发明人： Chandrika Prasad , Roy Yu , Richard L. Canull , Giulio DiGiacomo , Ajay P. Giri , Lewis S. Goldmann , Kimberley A. Kelly , Bouwe W. Leenstra , Voya R. Markovich , Eric D. Perfecto , Sampath Purushothaman , Joseph M. Sullivan
IPC分类号： H01R1204
CPC分类号： H01L21/6835 , H01L21/4857 , H01L23/16 , H01L23/49833 , H01L2221/68359 , H01L2221/68368 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H05K1/141 , H05K3/20 , H05K3/284 , H05K3/3436 , H05K3/467 , H05K7/023 , H05K2201/049 , H05K2201/10977 , H05K2201/2036 , H05K2203/0182 , Y02P70/613 , Y10T29/49126 , Y10T29/4913 , Y10T29/49133 , Y10T29/49144 , Y10T29/49149 , Y10T29/49165 , Y10T29/49169 , Y10T29/49174 , Y10T29/49211 , Y10T29/49213 , H01L2924/00 , H01L2924/00014
摘要： A structure for mounting electronic devices which uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.
摘要翻译：一种用于安装电子器件的结构，其使用插入在下面的载体和上覆薄膜之间的非导电兼容间隔物。间隔件包括通孔的图形，其与载体和薄膜的相对表面上的相对互连匹配。以这种方式，焊接连接可以在通孔中延伸，以将薄膜电连接到载体上并平滑地形。在用于形成结构的相关方法中，薄膜建立在第一牺牲载体上，然后在第二牺牲载体上进一步处理，以防止其在其加工期间变形，膨胀或以其它方式受到不利影响。使用封闭的焊料接合工艺形成薄膜和载体之间的焊接连接。间隔件与层压卡一起使用以在携带薄膜的卡的部分上产生热应力释放结构。

73. 发明授权

US6121069A Interconnect structure for joining a chip to a circuit card 有权
标题翻译：用于将芯片连接到电路卡的互连结构
公开(公告)号：US6121069A
公开(公告)日：2000-09-19
申请号：US390084
申请日：1999-09-03
申请人： Christina M. Boyko , Anthony P. Ingraham , Voya R. Markovich , David J. Russell
发明人： Christina M. Boyko , Anthony P. Ingraham , Voya R. Markovich , David J. Russell
IPC分类号： H01L21/60 , H01L23/485 , H05K3/34 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H05K3/3436 , H01L2224/13 , H01L2224/13023 , H01L2224/13099 , H01L2224/13111 , H01L2224/13609 , H01L2224/16 , H01L2224/16225 , H01L2224/274 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K2203/0435 , H05K2203/073 , H05K3/3463 , Y02P70/613
摘要： A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.
摘要翻译：焊料互连优选地使用富铅球，以将低温芯片附接到任何更高级别的封装衬底上。在使用标准工艺形成焊球之后，使用光致抗蚀剂形成球限制金属掩模。使用锡水溶液浸渍法将优选纯锡的薄盖层沉积在焊球的表面上。

74. 发明授权

US5528159A Method and apparatus for testing integrated circuit chips 失效
公开(公告)号：US5528159A
公开(公告)日：1996-06-18
申请号：US454458
申请日：1995-05-30
申请人： Richard G. Charlton , George C. Correia , Mark A. Couture , Gary R. Hill , Kibby B. Horsford , Anthony P. Ingraham , Michael D. Lowell , Voya R. Markovich , Gordon C. Osborne, Jr. , Mark V. Pierson
发明人： Richard G. Charlton , George C. Correia , Mark A. Couture , Gary R. Hill , Kibby B. Horsford , Anthony P. Ingraham , Michael D. Lowell , Voya R. Markovich , Gordon C. Osborne, Jr. , Mark V. Pierson
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28
CPC分类号： G01R31/2863 , G01R1/0483 , G01R1/07307 , G01R31/2886
摘要： A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

75. 发明授权

US5509557A Depositing a conductive metal onto a substrate 失效
标题翻译：将导电金属沉积到基底上
公开(公告)号：US5509557A
公开(公告)日：1996-04-23
申请号：US184930
申请日：1994-01-24
申请人： Lisa J. Jimarez , William H. Lawrence , Voya R. Markovich , Robert J. Owen , Carlos J. Sambucetti
发明人： Lisa J. Jimarez , William H. Lawrence , Voya R. Markovich , Robert J. Owen , Carlos J. Sambucetti
IPC分类号： C23C18/28 , C23C18/22 , C23C18/31 , H05K3/18 , H05K3/38 , B05D3/04 , C23F1/00
CPC分类号： H05K3/38 , C23C18/22 , H05K3/381 , H05K2203/1105 , H05K2203/1152 , H05K3/181
摘要： A method for depositing a conductive metal onto a dielectric substrate is provided. The method includes obtaining a metal sheet having a roughened surface that has the following parameters:R.sub.a =0.05-0.08 mil,R.sub.max =0.20-0.55 mil,S.sub.m =1.00-3.00 mil,R.sub.p =0.20-0.35 mil, andsurface area=0.90-1.20 square milswherein R.sub.a is the average roughness and the arithmetic mean of the departures from horizontal mean line profile;R.sub.max is the maximum peak-to-valley height;S.sub.m is the mean spacing between high spots at the mean line;R.sub.p is the maximum profile height from the mean line; andsurface area is the area under the surface profile from each measurement using a Talysurf S-120 profilometer;The sheet is laminated to the dielectric substrate surface by pressing the roughened surface of the metal sheet against the surface of the substrate and then removed from the substrate. The substrate surface is seeded to render it active for electroless plating thereon; and then a metal from an electroless plating bath is plated thereon.In another method, the dielectric substrate is seeded to render it active for electroless plating thereon. A metal is then plated thereon from an electroless plating bath. The plated metal is subjected to temperature of at least about 100 .degree. C. for a time sufficient to increase the adhesion of the metal to the substrate.
摘要翻译：提供了一种在电介质基片上沉积导电金属的方法。该方法包括获得具有以下参数的粗糙表面的金属片：Ra = 0.05-0.08密耳，Rmax = 0.20-0.55密耳，Sm = 1.00-3.00密耳，Rp = 0.20-0.35密耳，表面积= 0.90 -1.20平方米，其中Ra是平均粗糙度和离开水平平均线轮廓的算术平均值; Rmax是最大峰谷高度; Sm是平均线高点之间的平均间距; Rp是距平均线的最大轮廓高度; 表面积是使用Talysurf S-120轮廓仪进行每次测量的表面轮廓下面积; 通过将金属片的粗糙表面压在衬底的表面上，然后从衬底上去除，将片层压到电介质衬底表面上。将基材表面接种以使其活性以在其上进行无电镀; 然后将来自化学镀浴的金属镀在其上。在另一种方法中，将电介质基底接种以使其在其上进行无电镀。然后将金属从化学镀浴镀在其上。将电镀金属经受至少约100℃的温度足以增加金属与基底的粘合力的时间。

76. 发明授权

US5427895A Semi-subtractive circuitization 失效
标题翻译：半减法电路
公开(公告)号：US5427895A
公开(公告)日：1995-06-27
申请号：US172409
申请日：1993-12-23
申请人： Roy H. Magnuson , Richard W. Malek , Voya R. Markovich , William E. Wilson
发明人： Roy H. Magnuson , Richard W. Malek , Voya R. Markovich , William E. Wilson
IPC分类号： H05K3/10 , H05K3/24 , H05K3/42 , G03F7/00
CPC分类号： H05K3/427 , H05K3/108 , H05K2201/0355 , H05K2203/072 , H05K3/244
摘要： A process for selective plating of a metal onto a substrate surface is provided. The process includes laminating a layer of conductive metal onto a dielectric substrate; and providing thru holes extending through said layer of conductive metal and said dielectric substrate.A thin layer of conductive metal is plated on the walls of the thru holes; and a photoresist layer is applied to the surface of the conductive metal and selectively exposed and developed to provide a mask corresponding to the negative of the desired circuit pattern.The exposed metal that is not covered by the photoresist is removed and then the remaining photoresist is removed to thereby provide the desired circuit pattern. A conductive metal is plated on the pattern up to the desired thickness.
摘要翻译：提供了将金属选择性镀覆到基板表面上的工艺。该方法包括将导电金属层层压到电介质基底上; 并且提供穿过所述导电金属层和所述电介质基板的通孔。导电金属薄层镀在通孔的壁上; 并且将光致抗蚀剂层施加到导电金属的表面并选择性地暴露和显影以提供对应于期望电路图案的负值的掩模。去除未被光致抗蚀剂覆盖的暴露的金属，然后除去剩余的光致抗蚀剂，从而提供所需的电路图案。将导电金属镀在图案上达到所需厚度。

77. 发明授权

US5420520A Method and apparatus for testing of integrated circuit chips 失效
标题翻译：用于集成电路芯片测试的方法和装置
公开(公告)号：US5420520A
公开(公告)日：1995-05-30
申请号：US76069
申请日：1993-06-11
申请人： Morris Anschel , Anthony P. Ingraham , Charles R. Lamb , Michael D. Lowell , Voya R. Markovich , Wolfgang Mayr , Richard G. Murphy , Mark V. Pierson , Tamar A. Powers , Timothy S. Reny , Scott D. Reynolds , Bahgat G. Sammakia , Wayne R. Storr
发明人： Morris Anschel , Anthony P. Ingraham , Charles R. Lamb , Michael D. Lowell , Voya R. Markovich , Wolfgang Mayr , Richard G. Murphy , Mark V. Pierson , Tamar A. Powers , Timothy S. Reny , Scott D. Reynolds , Bahgat G. Sammakia , Wayne R. Storr
IPC分类号： G01R31/26 , G01R31/28 , H01L21/66 , H01R13/02 , G01R1/073 , G01R31/02
CPC分类号： G01R31/2863 , G01R31/2886 , G01R31/2862 , G01R31/287 , G01R31/2877 , G01R31/2879
摘要： A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.
摘要翻译：公开了一种测试半导体芯片的方法。单个半导体芯片具有I / O，电源和接地触点。在本发明的方法中，提供了一种芯片测试夹具系统。芯片测试夹具系统具有对应于半导体芯片上的触点的触点。载体触点具有树枝状表面。芯片触点与芯片测试夹具系统上的导体焊盘导电接触。测试信号输入矢量被施加到半导体芯片的输入，从半导体芯片恢复输出信号矢量。测试后，芯片从基板上取下。

78. 发明授权

US5191174A High density circuit board and method of making same 失效
标题翻译：高密度电路板及其制造方法
公开(公告)号：US5191174A
公开(公告)日：1993-03-02
申请号：US561401
申请日：1990-08-01
申请人： Chi S. Chang , Joseph G. Hoffarth , Voya R. Markovich , Keith A. Snyder , John P. Wiley
发明人： Chi S. Chang , Joseph G. Hoffarth , Voya R. Markovich , Keith A. Snyder , John P. Wiley
IPC分类号： H05K1/11 , H05K3/00 , H05K3/42 , H05K3/46
CPC分类号： H05K3/429 , H05K1/115 , H05K3/4614 , H05K3/462 , H05K3/4623 , H05K2201/0352 , H05K2201/09518 , H05K2201/09536 , H05K2201/096 , H05K2201/09845 , H05K2203/061 , H05K3/0032 , Y10T29/49126
摘要： A multilayered circuit board assembly which includes a plurality of layered subassemblies each having electrically conducting wiring and at least one through hole therein. A first of these subassemblies possesses a greater wiring dnesity than the others while a second subassembly possesses a lesser resistance (and wiring density) than the others. In one example, several (e.g. at least four) such layered subassemblies may be included in the overall assembly such that those layers located along one side of the board may possess substantially greater wiring densities than the layers on the other side of the board while those layers on said other side will in turn possess lesser resistance (and greater current capacities). There are also described at least three methods for making the above multilayered circuit board assembly. Such a structure may be utilized in supercomputer applications.

79. 发明授权

US4948707A Conditioning a non-conductive substrate for subsequent selective deposition of a metal thereon 失效
标题翻译：调节非导电基底，以便随后在其上选择性沉积金属
公开(公告)号：US4948707A
公开(公告)日：1990-08-14
申请号：US156519
申请日：1988-02-16
申请人： Robert W. Johnson , William H. Lawrence , Gary K. Lemon , Roy H. Magnuson , Voya R. Markovich , Ralph E. Parsons , Carlos J. Sambucetti
发明人： Robert W. Johnson , William H. Lawrence , Gary K. Lemon , Roy H. Magnuson , Voya R. Markovich , Ralph E. Parsons , Carlos J. Sambucetti
IPC分类号： C23C18/18 , C23C18/28 , C23C18/30 , H05K3/00 , H05K3/18 , H05K3/38
CPC分类号： H05K3/181 , H05K3/184 , H05K3/381 , H05K2203/0716 , H05K2203/1152 , H05K2203/122 , H05K2203/1407 , H05K3/0023
摘要： A non-conductive substrate is conditioned for subsequent selective deposition of a metal thereon by providing at least one of the major surfaces of the substrate in roughened form, contacting that surface(s) with a palladium/tin catalyst, activating the catalyst by employing an alkali hydroxide solution, laminating a photosensitive composition to the major surface(s), and exposing the photosensitive composition to actinic light in a predetermined pattern and then developing to provide the predetermined pattern.

80. 发明授权

US09451693B2 Electrically conductive adhesive (ECA) for multilayer device interconnects 有权
标题翻译：导电胶（ECA）用于多层器件互连
公开(公告)号：US09451693B2
公开(公告)日：2016-09-20
申请号：US13198756
申请日：2011-08-05
申请人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
发明人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
IPC分类号： H05K1/11 , H05K1/03
CPC分类号： H05K1/0313 , B23K26/382 , B23K26/40 , B23K2101/40 , B23K2103/16 , B23K2103/172 , B23K2103/52 , H01B1/22 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01322 , H01L2924/15311 , H05K1/097 , H05K3/4053 , H05K3/4069 , H05K3/462 , H05K3/4623 , H05K3/4641 , H05K2201/0257 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09718 , H05K2201/10378 , H05K2203/0425 , H05K2203/1152 , Y10T29/49128 , Y10T29/49165 , H01L2924/00
摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.
摘要翻译：用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。

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