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1. 发明授权

US09420689B2 Method of making a circuitized substrate 有权
标题翻译：制造电路化基板的方法
公开(公告)号：US09420689B2
公开(公告)日：2016-08-16
申请号：US12589239
申请日：2009-10-20
申请人： Rabindra N. Das , Michael J. Rowlands
发明人： Rabindra N. Das , Michael J. Rowlands
IPC分类号： H01K3/10 , H05K1/09
CPC分类号： H05K1/095 , H05K1/116 , H05K1/167 , H05K3/429 , H05K2203/0568 , Y10T29/49165
摘要： A circuitized substrate which utilizes at least one internal (embedded) resistor as part thereof, the resistor comprised of a material including resin and a quantity of powders of nano-particle and/or micro-particle sizes. The resistor serves to decrease the capacitance in the formed circuit while only slightly increasing the high frequency resistance, thereby improving circuit performance through the substantial elimination of some discontinuities known to exist in structures like these. An electrical assembly (substrate and at least one electrical component) is also provided.
摘要翻译：电路基板，其利用至少一个内部（嵌入式）电阻器作为其一部分，所述电阻器由包括树脂的材料和一定量的纳米颗粒和/或微粒尺寸的粉末构成。该电阻器用于降低形成的电路中的电容，同时仅稍微增加高频电阻，从而通过显着消除已知存在于这些结构中的一些不连续性来改善电路性能。还提供电气组件（基板和至少一个电气部件）。

2. 发明授权

US08685284B2 Conducting paste for device level interconnects 有权
标题翻译：用于器件级互连的导电膏
公开(公告)号：US08685284B2
公开(公告)日：2014-04-01
申请号：US12884657
申请日：2010-09-17
申请人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
发明人： Rabindra N. Das , Roy H. Magnuson , Mark D. Poliks , Voya R. Markovich
IPC分类号： H01B1/00 , H01B1/22 , H01B1/02
CPC分类号： H01B1/22 , H01L2224/81 , Y10T29/49117
摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.
摘要翻译：导电糊和形成用于器件级互连的糊的方法。导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。通常，小于5微米的平均片尺寸适用于五微米互连。然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。最终混合物中基于LMP的糊剂的量优选为20-50重量％。纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

3. 发明授权

US08558374B2 Electronic package with thermal interposer and method of making same 失效
标题翻译：具有热插入件的电子封装及其制造方法
公开(公告)号：US08558374B2
公开(公告)日：2013-10-15
申请号：US13022654
申请日：2011-02-08
申请人： Voya R. Markovich , Rabindra N. Das , Frank D. Egitto , James J. McNamara, Jr.
发明人： Voya R. Markovich , Rabindra N. Das , Frank D. Egitto , James J. McNamara, Jr.
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H05K7/1061 , H01L23/473 , H01L23/49833 , H01L23/5389 , H01L2924/0002 , H05K1/0203 , H05K2201/10378 , H01L2924/00
摘要： An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.
摘要翻译：具有夹在其间的插入件的两个电路化基板的电子封装件，所述插入器将基板电气互连，同时包括至少一个电气部件（例如，功率模块），其基本上在其中，以为所得到的封装提供甚至进一步的操作能力。

4. 发明授权

US08541687B2 Coreless layer buildup structure 有权
标题翻译：无芯层堆积结构
公开(公告)号：US08541687B2
公开(公告)日：2013-09-24
申请号：US12764993
申请日：2010-04-22
申请人： Voya Markovich , Timothy Antesberger , Frank D. Egitto , William Wilson , Rabindra N. Das
发明人： Voya Markovich , Timothy Antesberger , Frank D. Egitto , William Wilson , Rabindra N. Das
IPC分类号： H05K1/03 , H05K1/02 , H05K1/09
CPC分类号： H05K3/462 , H05K1/167 , H05K3/4069 , H05K3/4623 , H05K3/4632 , H05K2203/0191 , H05K2203/061 , H05K2203/063
摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin.
摘要翻译：一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。

5. 发明授权

US08499445B1 Method of forming an electrically conductive printed line 有权
标题翻译：形成导电印刷线的方法
公开(公告)号：US08499445B1
公开(公告)日：2013-08-06
申请号：US13184699
申请日：2011-07-18
申请人： Rabindra N. Das , Frank D. Egitto , Voya R. Markovich
发明人： Rabindra N. Das , Frank D. Egitto , Voya R. Markovich
IPC分类号： H05K3/40
CPC分类号： H05K3/246 , H05K3/1216 , H05K3/125 , H05K3/243 , H05K2201/0245 , H05K2203/0425 , H05K2203/072 , H05K2203/095 , Y10T29/49155 , Y10T29/49156 , Y10T29/49162 , Y10T29/49165
摘要： Printed conductive lines and a method of preparing them using polymer nanocomposites with low resistivity and high current carrying capacity. Plasma treatment selectively removes polymers/organics from nanocomposites. Subsequent selective metal is deposited on top of the exposed metal surface of the printed conductive lines in order to improve current carrying capacity of the conductive printed lines. The printed conductive lines use a conductive ink or printing process and are then cured thermally and/or by a lamination process. Next, the printed conductive lines are treated with the plasma for 5-15 minutes in order to remove organics. E-less copper (Cu) is selectively deposited only at the conducting particle surface of the printed conductive lines. If desired, e-less gold, silver, tin, or tin-lead can be deposited on top of the e-less Cu.
摘要翻译：印刷导电线及其使用具有低电阻率和高载流能力的聚合物纳米复合材料制备它们的方法。等离子体处理选择性地从纳米复合材料中除去聚合物/有机物。随后的选择性金属沉积在印刷导线的暴露的金属表面的顶部上，以便改善导电印刷线的载流能力。印刷的导线使用导电油墨或印刷工艺，然后热固化和/或通过层压工艺固化。接下来，印刷的导线用等离子体处理5-15分钟以除去有机物。仅在印刷导线的导电粒子表面选择性地沉积无电铜（Cu）。如果需要，可以在无电镀铜的顶部上沉积无电镀金，银，锡或锡铅。

6. 发明申请

US20130033827A1 ELECTRICALLY CONDUCTIVE ADHESIVE (ECA) FOR MULTILAYER DEVICE INTERCONNECTS 有权
标题翻译：用于多层设备互连的电导体粘合剂（ECA）
公开(公告)号：US20130033827A1
公开(公告)日：2013-02-07
申请号：US13198756
申请日：2011-08-05
申请人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
发明人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
IPC分类号： H05K5/00 , H05K1/09 , B23K31/02 , H05K1/00 , H01B1/00 , H01B1/02
CPC分类号： H05K1/0313 , B23K26/382 , B23K26/40 , B23K2101/40 , B23K2103/16 , B23K2103/172 , B23K2103/52 , H01B1/22 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01322 , H01L2924/15311 , H05K1/097 , H05K3/4053 , H05K3/4069 , H05K3/462 , H05K3/4623 , H05K3/4641 , H05K2201/0257 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09718 , H05K2201/10378 , H05K2203/0425 , H05K2203/1152 , Y10T29/49128 , Y10T29/49165 , H01L2924/00
摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.
摘要翻译：用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。

7. 发明授权

US08240031B2 Method of joining a semiconductor device/chip to a printed wiring board 有权
标题翻译：将半导体器件/芯片接合到印刷线路板的方法
公开(公告)号：US08240031B2
公开(公告)日：2012-08-14
申请号：US12837640
申请日：2010-07-16
申请人： Voya R. Markovich , Ronald V. Smith , How T. Lin , Frank D. Egitto , Rabindra N. Das , William E. Wilson , Rajinder S. Rai
发明人： Voya R. Markovich , Ronald V. Smith , How T. Lin , Frank D. Egitto , Rabindra N. Das , William E. Wilson , Rajinder S. Rai
IPC分类号： H05K3/30
CPC分类号： H05K3/3436 , H05K1/111 , H05K2201/10378 , Y02P70/613 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/4919
摘要： A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.
摘要翻译：柔性，高密度贴花及其在柔性芯片载体和印刷线路板之间形成可拆卸电互连的方法。柔性贴花在第一表面上具有细间距焊盘，并且在第二表面上具有比微细间距更宽的间距的焊盘，设计成电连接到半导体器件的第一表面上的细间距焊盘和较宽间距第二表面上的焊盘被设计成电连接到印刷线路板等。第一表面上的焊盘通过柔性贴花中的一个或多个绝缘水平导电地连接到第二表面上的焊盘。

8. 发明申请

US20120160544A1 CORELESS LAYER BUILDUP STRUCTURE WITH LGA 有权
标题翻译：无缝层建筑结构与LGA
公开(公告)号：US20120160544A1
公开(公告)日：2012-06-28
申请号：US12764994
申请日：2010-04-22
申请人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
发明人： Timothy Antesberger , Rabindra N. Das , Frank D. Egitto , Voya R. Markovich , William E. Wilson
IPC分类号： H05K1/00 , H05K1/09 , H05K1/03
CPC分类号： H05K3/4623 , H05K1/092 , H05K3/4053 , H05K3/4614 , H05K3/4691 , H05K2203/061
摘要： A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.
摘要翻译：一种用于PCB或PWB板的衬底，其具有无芯堆积层和至少一个金属和至少一个介电层。无芯堆积电介质层可由至少部分固化的热固性树脂和热塑性树脂组成。衬底还可以包含焊盘阵列（LGA）封装。

9. 发明申请

US20110043987A1 METHOD OF MAKING CIRCUITIZED SUBSTRATE WITH RESISTOR INCLUDING MATERIAL WITH METAL COMPONENT AND ELECTRICAL ASSEMBLY AND INFORMATION HANDLING SYSTEM UTILIZING SAID CIRCUITIZED SUBSTRATE 失效
标题翻译：使用包含金属部件的材料制成电路的电路基板的方法以及利用所述电路基板的电气装置和信息处理系统
公开(公告)号：US20110043987A1
公开(公告)日：2011-02-24
申请号：US12938759
申请日：2010-11-03
申请人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich
发明人： Rabindra N. Das , John M. Lauffer , Voya R. Markovich
IPC分类号： G06F1/16 , H05K7/00 , B82Y30/00
CPC分类号： H05K1/167 , H01G4/206 , H01L2224/16 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/0102 , H01L2924/01025 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H05K1/095 , H05K1/162 , H05K3/0023 , H05K2201/0187 , H05K2201/0209 , H05K2201/0215 , H05K2201/0257 , H05K2203/1453 , Y10T29/49082 , Y10T29/49087 , Y10T29/49089 , Y10T29/49091 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.
摘要翻译：一种制造电路化基板的方法，包括由包括聚合物树脂的材料和包括至少一种金属组分和至少一种陶瓷组分的混合物的纳米粉末的量组成的电阻器。陶瓷部件可以是铁电陶瓷和/或高表面积陶瓷和/或透明氧化物和/或掺杂亚锰酸盐。或者，材料将包括聚合物树脂和纳米粉末，其中纳米粉末包含至少一种金属涂覆的陶瓷和/或至少一种氧化物涂覆的金属组分。还提供了使用这种电路化基板的电气组件（基板和至少一个电气部件）以及信息处理系统（例如，个人计算机）。

10. 发明授权

US07449381B2 Method of making a capacitive substrate for use as part of a larger circuitized substrate, method of making said circuitized substrate and method of making an information handling system including said circuitized substrate 有权
标题翻译：制造用作较大电路基板的一部分的电容基板的方法，制造所述电路化基板的方法和制造包括所述电路化基板的信息处理系统的方法
公开(公告)号：US07449381B2
公开(公告)日：2008-11-11
申请号：US11352279
申请日：2006-02-13
申请人： Rabindra N. Das , John M. Lauffer , How T. Lin , Voya R. Markovich
发明人： Rabindra N. Das , John M. Lauffer , How T. Lin , Voya R. Markovich
IPC分类号： H01L21/8234 , H01L21/00
CPC分类号： H05K1/162 , H05K1/113 , H05K3/0023 , H05K3/4602 , H05K2201/0187 , H05K2201/0209 , H05K2201/09309 , H05K2201/09509 , H05K2201/09536 , H05K2203/013 , H05K2203/0568
摘要： A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.
摘要翻译：一种形成电容衬底的方法，其中材料的至少一个电容介电层被屏幕或喷墨印刷到导体上，然后进一步处理衬底，包括添加通孔以将所选择的元件耦合到衬底内以形成至少两个电容器作为衬底的内部元件。电容性衬底可以结合在更大的电路化衬底内，例如以形成电组件。还提供了一种制造包括这种基板的信息处理系统的方法。

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