专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20170162275A1 COMPENSATION CIRCUIT FOR COMPENSATING FOR AN INPUT CHARGE IN A SAMPLE AND HOLD CIRCUIT 审中-公开
公开(公告)号：US20170162275A1
公开(公告)日：2017-06-08
申请号：US15363160
申请日：2016-11-29
申请人： NXP USA, Inc.
发明人： Yuan Gao , Jerome Jean Pierre Luc Casters , Stephane Laurant Michel Ollitrault
IPC分类号： G11C27/02 , H02J7/00 , H03M1/12
CPC分类号： G11C27/026 , G01R31/36 , H02J7/0021
摘要： A compensation circuit for compensating for an input charge at a first input of a sample and hold circuit, comprising: a first buffer, a first compensation capacitor comprising a first compensation terminal switchable between a first buffer input and a first buffer output, and a second compensation terminal switchable between the first buffer output and a reference terminal, and a control circuit to switch the first compensation terminal to the first buffer output and the second compensation terminal to the reference terminal during sampling, for storing a compensation charge into the first compensation capacitor, and to switch the first compensation terminal to the first buffer input and the second compensation terminal to the first buffer output during holding, for discharging the first compensation capacitor into the first input. The compensation charge is substantially equal to the input charge.

72. 发明授权

US09658642B2 Timing control for unmatched signal receiver 有权
公开(公告)号：US09658642B2
公开(公告)日：2017-05-23
申请号：US14038537
申请日：2013-09-26
申请人： Intel Corporation
发明人： Christopher P. Mozak
IPC分类号： G06F1/00 , H04L7/00 , G06F1/04 , G11C7/22 , H03L7/00 , G11C27/02
CPC分类号： G06F1/04 , G06F13/4291 , G11C7/222 , G11C27/02 , H03L7/00 , H04L7/0008
摘要： A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.

73. 发明申请

US20170125124A1 CHARGE INJECTION NOISE REDUCTION IN SAMPLE-AND-HOLD CIRCUIT 有权
公开(公告)号：US20170125124A1
公开(公告)日：2017-05-04
申请号：US14928524
申请日：2015-10-30
申请人： Sony Semiconductor Solutions Corporation
发明人： Noam Eshel , Golan Zeituni , Zvika Lupu
IPC分类号： G11C27/02
CPC分类号： G11C27/02 , G11C27/024
摘要： A sample-and-hold circuit includes a first transistor; a second transistor disposed between a gate electrode and a drain electrode of the first transistor; a sampling capacitor, an electrode of the sampling capacitor being connected to the gate electrode of the first transistor; and a first current source connected to the drain electrode of the first transistor, where a gate electrode of the second transistor receives a gate control signal. A minimum voltage of the gate control signal is Vth2+Vsat2+Vth1+Vsat1, where Vth1 is a threshold voltage of the first transistor, Vsat1 is a saturation voltage of the first transistor, Vth2 is a threshold voltage of the second transistor, and Vsat2 is a saturation voltage of the second transistor.

74. 发明授权

US09621157B2 Sampling circuit and sampling method 有权
公开(公告)号：US09621157B2
公开(公告)日：2017-04-11
申请号：US14957327
申请日：2015-12-02
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Ming-Cheng Chiang , Li-Lung Kao
IPC分类号： H03K17/687 , G11C27/00 , G11C27/02
CPC分类号： H03K17/6872 , G11C27/00 , G11C27/026 , H03K2217/0054
摘要： A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.

75. 发明申请

US20170098475A1 SAMPLING DEVICE 审中-公开
公开(公告)号：US20170098475A1
公开(公告)日：2017-04-06
申请号：US15173348
申请日：2016-06-03
申请人： Rohde & Schwarz GmbH & Co. KG
发明人： Ols HIDRI
IPC分类号： G11C27/02 , H03K5/24
CPC分类号： G11C27/02 , G11C27/024 , H03K5/2418 , H03K5/2427 , H03K5/2481 , H03K5/249 , H03M1/124
摘要： A sampling device samples a differential measuring voltage. The sampling device comprises a first holding device, a second holding device and a multiplexing circuit, which is configured to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device, at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device, at each LOW-value of the second clock signal. The sampling device comprises a reset device configured to reset the second holding device at or after each HIGH-value of the second clock signal and reset the first holding device at or after each LOW-value of the second clock signal.

76. 发明授权

US09614538B1 Analog-to-digital conversion based on signal prediction 有权
公开(公告)号：US09614538B1
公开(公告)日：2017-04-04
申请号：US15243626
申请日：2016-08-22
申请人： 9011579 Canada Incorporée
发明人： Masum Hossain , Maruf H. Mohammad
IPC分类号： H04L7/00 , H03M1/00 , H04L7/033 , H04L25/03 , G11C27/02 , H03L7/08 , H03M1/12
CPC分类号： H03M1/002 , G05F1/10 , G11C27/02 , H03L7/0807 , H03M1/124 , H03M1/1245 , H03M1/1255 , H03M1/361 , H03M1/38 , H04L7/0087 , H04L7/033 , H04L7/0332 , H04L7/0334 , H04L25/03006 , H04L25/06
摘要： Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

77. 发明申请

US20170085821A1 DUAL SAMPLE-AND-HOLD CIRCUIT WITH RESISTIVE GAIN 审中-公开
公开(公告)号：US20170085821A1
公开(公告)日：2017-03-23
申请号：US15356500
申请日：2016-11-18
申请人： Sony Semiconductor Solutions Corporation
发明人： Noam Eshel , Golan Zeituni
IPC分类号： H04N5/378 , G11C27/02
CPC分类号： H04N5/378 , G11C27/024 , H02M11/00 , H03M3/30 , H04N5/374
摘要： An image processing circuit includes a first dual sample-and-hold circuit that samples a first data and a second data from a first pixel, a second dual sample-and-hold circuit that samples a third data and a fourth data from a second pixel, a voltage-to-current circuit including a resistor and a current source, that receives the first data and the second data to output a first difference data, and that receives the third data and the fourth data to output a second difference data; and an analog-to-digital converter that converts the first and second difference data from an analog form to a digital form.

78. 发明授权

US09600427B2 Receiver circuit and semiconductor integrated circuit 有权
公开(公告)号：US09600427B2
公开(公告)日：2017-03-21
申请号：US14837870
申请日：2015-08-27
申请人： Socionext Inc.
发明人： Masahiro Kudo
IPC分类号： G11C7/10 , G11C7/06 , G06F13/38 , H04L1/00 , G06F13/40 , H04L7/00 , H04L25/03 , G11C27/02
CPC分类号： G06F13/38 , G06F13/4072 , G11C27/02 , H04L1/0045 , H04L7/0087 , H04L25/03
摘要： A receiver circuit includes: a plurality of first holding circuits respectively latching a plurality of reception data pieces on the basis of a same clock signal; a comparison circuit respectively comparing first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; and a plurality of second holding circuits respectively latching the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical.

79. 发明申请

US20170076823A1 TRACK AND HOLD WITH ACTIVE CHARGE CANCELLATION 审中-公开
标题翻译：跟踪和保持有效充电取消
公开(公告)号：US20170076823A1
公开(公告)日：2017-03-16
申请号：US15261303
申请日：2016-09-09
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Himanshu AGGRAWAL , Manar Ibrahim EL-CHAMMAS
IPC分类号： G11C27/02
CPC分类号： G11C27/024
摘要： A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.
摘要翻译：轨道保持电路包括初级采样电容器，初级开关晶体管和消除晶体管。主开关晶体管被配置为提供将输入信号连接到初级采样电容器的轨道状态和将初级采样电容器的输入信号隔离的保持状态。消除晶体管耦合到初级采样电容器。取消晶体管被配置为在初级开关晶体管处于保持状态时，通过初级开关晶体管将主要采样电容器上的电荷注入到主要采样电容器上，从而抵消初级采样电容器的注入。

80. 发明授权

US09577614B2 Detecting method and device for suppressing interference of low-frequency noise 有权
标题翻译：用于抑制低频噪声干扰的检测方法和装置
公开(公告)号：US09577614B2
公开(公告)日：2017-02-21
申请号：US13889436
申请日：2013-05-08
申请人： EGALAX_EMPIA TECHNOLOGY INC.
发明人： Chin-Fu Chang , Shang-Tai Yeh , Guang-Huei Lin , Po-Chuan Lin
IPC分类号： G06F3/045 , H03K3/013 , G06F3/044 , G11C27/02 , G06F3/041 , G06F3/0354
CPC分类号： H03K3/013 , G06F3/03545 , G06F3/0418 , G06F3/044 , G11C27/026
摘要： The invention detects the difference between the maximum signal and the minimum signal at each of a plurality of cycles separately when a sine wave is received. All differences are summed for generating a single detected signal for suppressing the interference of low-frequency noise. No synchronization with the sine wave is necessary and the detection can start at any phase of the sine wave.
摘要翻译：本发明在接收到正弦波时分别检测多个周期中的每个周期的最大信号和最小信号之间的差异。将所有差值相加以产生用于抑制低频噪声干扰的单个检测信号。不需要与正弦波同步，并且检测可以在正弦波的任何阶段开始。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式