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71. 发明授权

US07687886B2 High on-state breakdown heterojunction bipolar transistor 有权
标题翻译：高导通状态击穿异质结双极晶体管
公开(公告)号：US07687886B2
公开(公告)日：2010-03-30
申请号：US11153078
申请日：2005-06-14
申请人： Noren Pan , Andree Wibowo
发明人： Noren Pan , Andree Wibowo
IPC分类号： H01L27/082
CPC分类号： H01L29/0817 , H01L29/0821 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
摘要翻译：异相结双极晶体管（HBT）具有改善的导通状态击穿电压VCE。 HBT的导通状态击穿电压的改善提高了HBT的输出功率特性和HBT承受大阻抗失配（大VSWR）的能力。导通状态击穿电压的改善与抑制形成HBT的集电极区域的集电极层和副集电极层的接合附近的高电场有关。

72. 发明申请

US20100032720A1 SEMICONDUCTOR DEVICE AND RADIO COMMUNICATION DEVICE 有权
标题翻译：半导体器件和无线电通信设备
公开(公告)号：US20100032720A1
公开(公告)日：2010-02-11
申请号：US12579975
申请日：2009-10-15
申请人： Satoshi SASAKI , Yasunari Umemoto , Yasuo Osone , Tsutomu Kobori , Chushiro Kusano , Isao Ohbu , Kenji Sasaki
发明人： Satoshi SASAKI , Yasunari Umemoto , Yasuo Osone , Tsutomu Kobori , Chushiro Kusano , Isao Ohbu , Kenji Sasaki
IPC分类号： H01L27/082 , H01L23/52
CPC分类号： H01L29/7304 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/042 , H01L27/0605 , H01L27/067 , H01L28/40 , H01L29/0808 , H01L29/7371 , H01L2223/6627 , H01L2223/6644 , H01L2224/05553 , H01L2224/05554 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48227 , H01L2224/48235 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01041 , H01L2924/01042 , H01L2924/01049 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/10336 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1423 , H01L2924/19032 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2224/45099
摘要： A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
摘要翻译：提供了允许半导体器件的热阻降低和小型化的技术。半导体器件具有多个单位晶体管Q，每个具有单位晶体管Q的第一数量（例如七个）的晶体管形成区域3a，3b和3e以及每个具有第二数量的晶体管形成区域3c和3d（例如，，四个）单位晶体管Q.晶体管形成区域3c和3d位于晶体管形成区域3a，3b，3e和3f之间，并且第一数量大于第二数量。

73. 发明授权

US07605446B2 Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation 失效
标题翻译：具有第一和第二绝缘门控的双极高压/功率半导体器件和操作方法
公开(公告)号：US07605446B2
公开(公告)日：2009-10-20
申请号：US11486377
申请日：2006-07-14
申请人： Florin Udrea , Nishad Udugampola , Gehan A. J. Amaratunga
发明人： Florin Udrea , Nishad Udugampola , Gehan A. J. Amaratunga
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L23/58
CPC分类号： H01L29/7393 , H01L29/0657 , H01L29/0696 , H01L29/4232 , H01L29/7394 , H01L2924/0002 , H01L2924/00
摘要： A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.
摘要翻译：双极高压/功率半导体器件具有分别具有与其不同导电类型的端部区域相邻的漂移区域。提供高低压端子。还提供了第一绝缘栅极端子和第二绝缘栅极端子。一个或多个驱动电路为第一和第二绝缘栅极端子提供适当的电压，以允许在与第一方向相反的第一方向或第二方向上的电流传导。

74. 发明申请

US20090194792A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090194792A1
公开(公告)日：2009-08-06
申请号：US12413010
申请日：2009-03-27
申请人： Satoru Konishi , Tsuneo Endo , Hirokazu Nakajima , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura , Atsushi Kurokawa
发明人： Satoru Konishi , Tsuneo Endo , Hirokazu Nakajima , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura , Atsushi Kurokawa
IPC分类号： H01L27/082 , H01L23/498
CPC分类号： H01L29/4933 , H01L21/84 , H01L23/4824 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L29/456 , H01L29/7835 , H01L2224/1403 , H01L2224/16235 , H01L2224/1703 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.
摘要翻译：半导体器件具有在布线基板的下表面上形成的用于GND的外部布线。连接到GND的外部配线的多个通孔形成为穿透布线基板。包括HBT的高功率的第一半导体芯片安装在布线基板的主表面上。第一半导体芯片的发射极电极与形成在第一半导体芯片中的多个HBT的发射极共同连接。发射极电极沿HBT排列的方向延伸。第一半导体芯片安装在布线基板上，使得多个通孔与发射极电极连接。散热值比第一半导体芯片低的第二半导体芯片安装在第一半导体芯片上。

75. 发明授权

US07564117B2 Bipolar transistor having variable value emitter ballast resistors 有权
标题翻译：具有可变值发射极镇流电阻的双极晶体管
公开(公告)号：US07564117B2
公开(公告)日：2009-07-21
申请号：US11957197
申请日：2007-12-14
申请人： James D. Beasom
发明人： James D. Beasom
IPC分类号： H01L27/082
CPC分类号： H01L29/7304 , H01L27/0658 , H01L27/067
摘要： Methods of forming and structures of a relatively large bipolar transistor is provided. The method includes forming a collector in a semiconductor region. Forming a base contiguous with a portion of the collector. Forming a plurality of emitters contiguous with portions of the base. Forming a common emitter interconnect and forming ballast emitter resistors for select emitters. Each ballast emitter resistor is coupled between an associated emitter and the common emitter interconnect. Each ballast resistor is further formed to have a selected resistance value. The selected resistance value of each ballast resistor is selected so the values of the ballast resistors vary in a two dimensional direction in relation to a working surface of the bipolar transistor.
摘要翻译：提供了相对较大的双极晶体管的形成方法和结构。该方法包括在半导体区域中形成集电极。形成与收集器的一部分相邻的基座。形成与基部的部分相邻的多个发射器。形成公共发射极互连，并形成用于选择发射极的镇流发射极电阻。每个镇流发射极电阻耦合在相关的发射极和公共发射极互连之间。每个镇流电阻器进一步形成为具有选定的电阻值。选择每个镇流电阻器的所选电阻值，使得镇流电阻器的值相对于双极晶体管的工作表面在二维方向上变化。

76. 发明授权

US07495313B2 Germanium substrate-type materials and approach therefor 有权
标题翻译：锗衬底型材料及其方法
公开(公告)号：US07495313B2
公开(公告)日：2009-02-24
申请号：US11188140
申请日：2005-07-22
申请人： Ammar Munir Nayfeh , Chi On Chui , Krishna C. Saraswat , Takao Yonehara
发明人： Ammar Munir Nayfeh , Chi On Chui , Krishna C. Saraswat , Takao Yonehara
IPC分类号： H01L27/082
CPC分类号： H01L29/518 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/2807 , H01L21/28255 , H01L29/16 , H01L29/165 , H01L29/513 , H01L29/66575 , H01L29/94
摘要： Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
摘要翻译：锗电路型结构方便。在一个示例实施例中，实施多步生长和退火工艺以在包括硅（Si）或含硅材料的衬底上生长含锗（Ge）的材料，例如异质外延锗。在某些应用中，缺陷通常被限制在硅/锗界面附近，通常阻止含锗材料的上表面的缺陷穿线。这些方法适用于包括锗MOS电容器，pMOSFET和光电器件在内的各种器件。

77. 发明授权

US07462923B1 Bipolar transistor formed using selective and non-selective epitaxy for base integration in a BiCMOS process 有权
标题翻译：使用选择性和非选择性外延法在BiCMOS工艺中进行基极整合形成的双极晶体管
公开(公告)号：US07462923B1
公开(公告)日：2008-12-09
申请号：US11899850
申请日：2007-09-08
申请人： Greg D. U'Ren
发明人： Greg D. U'Ren
IPC分类号： H01L27/082
CPC分类号： H01L29/732 , H01L21/8249 , H01L29/1004 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer extends over the first and second isolation regions. The bipolar transistor further includes a base layer situated on the epitaxial extension layer, where the base layer includes an epitaxial base, and where the epitaxial base includes a usable emitter formation area. The active area has a first width and the usable emitter formation area has a second width, where the second width is at least as large as the first width.
摘要翻译：根据一个示例性实施例，双极晶体管包括位于衬底中的第一和第二隔离区之间的有源区。双极晶体管还包括位于有源区上的外延延伸层，其中外延延伸层在第一和第二隔离区上延伸。双极晶体管还包括位于外延延伸层上的基极层，其中基极层包括外延基极，并且其中外延基底包括可用的发射极形成区域。有源区域具有第一宽度，并且可用的发射体形成区域具有第二宽度，其中第二宽度至少与第一宽度一样大。

78. 发明授权

US07459766B2 Semiconductor bipolar transistor 有权
标题翻译：半导体双极晶体管
公开(公告)号：US07459766B2
公开(公告)日：2008-12-02
申请号：US11392613
申请日：2006-03-30
申请人： Shuji Fujiwara
发明人： Shuji Fujiwara
IPC分类号： H01L27/082
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7322
摘要： A semiconductor device including a bipolar transistor in which the collector resistance. The bipolar transistor includes a first conduction type semiconductor substrate having a main surface. A second conduction type collector region is formed in the semiconductor substrate. A shallow trench isolation structure isolates the main surface of the semiconductor substrate into two insulated active regions. A collector leading portion is formed in one of the active regions. A first conduction type base region and a second conduction type emitter region are formed on the other one of the active regions. The collector region has a first depth from the main surface immediately below the shallow trench isolation structure, and the collector region has a second depth from the main surface immediately below the two active regions. The first depth is less than the second depth.
摘要翻译：一种半导体器件，包括集电极电阻的双极晶体管。双极晶体管包括具有主表面的第一导电型半导体衬底。在半导体衬底中形成第二导电型集电极区域。浅沟槽隔离结构将半导体衬底的主表面隔离成两个绝缘的有源区。集电极引导部分形成在一个有源区中。第一导电型基极区域和第二导电型发射极区域形成在另一个有源区域上。集电极区域具有从浅沟槽隔离结构正下方的主表面的第一深度，并且集电极区域具有紧邻两个活性区域的主表面的第二深度。第一个深度小于第二个深度。

79. 发明申请

US20080203379A1 ARRAY OF VERTICAL BIPOLAR JUNCTION TRANSISTORS, IN PARTICULAR SELECTORS IN A PHASE CHANGE MEMORY DEVICE 有权
标题翻译：垂直双极性晶体管的阵列，相变存储器件中的特定选择器
公开(公告)号：US20080203379A1
公开(公告)日：2008-08-28
申请号：US12037766
申请日：2008-02-26
申请人： Michele Magistretti , Fabio Pellizzer , Augusto Benvenuti
发明人： Michele Magistretti , Fabio Pellizzer , Augusto Benvenuti
IPC分类号： H01L45/00 , H01L27/082 , H01L21/8222
CPC分类号： H01L27/1022 , H01L21/76205 , H01L21/76224 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.
摘要翻译：一种用于制造双极晶体管阵列的方法，其中介电材料的深场绝缘区形成在半导体本体中，从而限定出彼此绝缘的多个有源区，并且在每个有源区中形成多个双极晶体管。特别地，在每个有源区域中，在半导体本体的表面一定距离处形成第一导电区域; 在第一导电区域上形成控制区域; 并且在每个控制区域中形成至少两个第二导电区域和至少一个控制接触区域。控制接触区域介于第二导电区域之间，并且至少两个表面场绝缘区域在控制接触区域和第二导电区域之间的每个有效区域中热生长。

80. 发明申请

US20080150082A1 POWER TRANSISTOR FEATURING A DOUBLE-SIDED FEED DESIGN AND METHOD OF MAKING THE SAME 有权
标题翻译：功率晶体管具有双面进料设计及其制造方法
公开(公告)号：US20080150082A1
公开(公告)日：2008-06-26
申请号：US11671035
申请日：2007-02-05
申请人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
发明人： Dragan Zupac , Sandra J. Wipf , Theresa M. Keller , Elizabeth C. Glass
IPC分类号： H01L27/082
CPC分类号： H01L29/73 , H01L23/4824 , H01L24/13 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/7322 , H01L2224/16 , H01L2924/19043 , H01L2924/30107
摘要： A power transistor (210) comprises a plurality of unit cell devices (212), a base contact configuration, an emitter contact configuration, and a collector contact configuration. The plurality of unit cell devices is arranged along an axis (194), each unit cell device including base (80), emitter (82), and collector (84) portions. The base contact configuration includes (i) a first base feed (150) coupled to the base portion of each unit cell device via a first end of at least one base finger (154) associated with a corresponding unit cell device and (ii) a second base feed (152) coupled to the base portion of each unit cell device via an opposite end of the at least one base finger associated with the corresponding unit cell device. The emitter contact configuration includes (i) a first emitter feed (172) coupled to the emitter portion of each unit cell device via a first end of an emitter metallization (176) associated with a corresponding unit cell device and (ii) a second emitter feed (174) coupled to the emitter portion of each unit cell device via an opposite end of the emitter metallization associated with the corresponding unit cell device. The collector contact configuration includes a collector feed (188) coupled to the collector portion of each unit cell device.
摘要翻译：功率晶体管（210）包括多个单位电池器件（212），基极触点配置，发射极触点配置和集电极触点配置。多个单电池器件沿轴线（194）布置，每个单元电池器件包括基极（80），发射极（82）和集电极（84）部分。基本接触配置包括：（i）经由与相应的单位电池器件相关联的至少一个基本手指（154）的第一端耦合到每个单元电池器件的基座部分的第一基本馈电（150）和（ii）第二基本馈送（152），其经由与所述对应的单元设备相关联的所述至少一个基本指的相对端耦合到每个单元单元设备的基本部分。发射极接触配置包括：（i）经由与相应的单位电池器件相关联的发射极金属化（176）的第一端耦合到每个单位电池器件的发射极部分的第一发射极馈电（172）和（ii）第二发射极馈电（174）经由与相应的单位电池器件相关联的发射极金属化的相对端耦合到每个单位电池器件的发射极部分。集电极接触配置包括耦合到每个单位电池器件的集电极部分的集电极馈送（188）。

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