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71. 发明授权

US06967520B2 Gate drive circuit, which makes the gate-charge flow back to the load and the main power source 失效
标题翻译：栅极驱动电路，使栅极电荷流回负载和主电源
公开(公告)号：US06967520B2
公开(公告)日：2005-11-22
申请号：US10683588
申请日：2003-10-14
申请人： Nobuyoshi Takehara
发明人： Nobuyoshi Takehara
IPC分类号： H02M1/08 , H02M3/158 , H02M3/335 , H03K17/00 , H03K17/04 , H03K17/0412 , H03K17/567 , H03K17/687
CPC分类号： H03K17/567 , H02M3/1588 , H03K17/0406 , H03K17/04123 , H03K17/687 , H03K2217/0036 , Y02B70/1466
摘要： A gate driving circuit having: a direct current power source; a driving signal source for outputting signal; a main switch device, having a gate terminal in which the signal outputted from the driving signal source is inputted, for controlling a conduction state between a source terminal and a drain terminal; a load energized when the conduction state between the source and drain terminals becomes a conductive state; a reverse current blocking unit, connected between the driving signal source and the gate terminal; and a regenerative unit, connected between the gate terminal and a high potential side of the power source, which becomes a conductive state when the conduction state between the source and drain terminals is a non-conductive state. A gate-source threshold voltage to obtain the conductive state between the source and drain terminals is set higher than an output voltage of the power source.
摘要翻译：一种栅极驱动电路，具有：直流电源; 用于输出信号的驱动信号源; 主开关装置，具有输入从驱动信号源输出的信号的栅极端子，用于控制源极端子和漏极端子之间的导通状态; 当源极和漏极端子之间的导通状态变为导通状态时，负载通电; 连接在驱动信号源和栅极端子之间的反向电流阻断单元; 以及连接在电源的栅极端子和高电位侧之间的再生单元，当源极和漏极端子之间的导通状态是非导通状态时，该再生单元变为导通状态。用于获得源极和漏极端子之间的导通状态的栅极 - 源极阈值电压被设置为高于电源的输出电压。

72. 发明授权

US06958631B2 High-speed current switch circuit 有权
标题翻译：高速电流开关电路
公开(公告)号：US06958631B2
公开(公告)日：2005-10-25
申请号：US10168572
申请日：2001-12-21
申请人： Yusuke Aiba , Masaki Ikeda , Takeshi Fujita , Hideaki Hirose , Akio Maruo
发明人： Yusuke Aiba , Masaki Ikeda , Takeshi Fujita , Hideaki Hirose , Akio Maruo
IPC分类号： H03K17/04 , G11B7/125 , H03K17/0412 , H03K17/687
CPC分类号： H03L7/02 , G11B7/126 , H03K17/04123
摘要： A high-speed current switch circuit of this invention has an n-type MOS transistor Q11 which switches and outputs a current, and a control circuit 11 which performs switching control of the MOS transistor Q11. In the control circuit 11, a source follower is formed by an N-type MOS transistor Q12 and a constant current source I2 which is a load on this transistor. A switch SW11 is connected to the MOS transistor Q12 to perform switching control of a current flowing through the MOS transistor Q12. The control circuit 11 includes a switch SW12 capable of grounding the gate of the MOS transistor 11. The source of the MOS transistor Q12 is connected to the gate of the MOS transistor Q11. Thus, even if a large current is caused to flow through the output transistor, the output transistor can be made to operate for switching at a high speed.
摘要翻译：本发明的高速电流开关电路具有切换并输出电流的n型MOS晶体管Q 11和执行MOS晶体管Q 11的开关控制的控制电路11。在控制电路11中，源极跟随器由N型MOS晶体管Q 12和作为该晶体管上的负载的恒流源I 2形成。开关SW 11连接到MOS晶体管Q 12，以对流过MOS晶体管Q12的电流进行开关控制。控制电路11包括能够使MOS晶体管11的栅极接地的开关SW 12。 MOS晶体管Q12的源极连接到MOS晶体管Q11的栅极。因此，即使使大电流流过输出晶体管，也可以使输出晶体管进行高速切换。

73. 发明申请

US20050179471A1 VERSATILE SYSTEM FOR CONTROLLING DRIVER SIGNAL TIMING 有权
标题翻译：用于控制驱动信号时序的多功能系统
公开(公告)号：US20050179471A1
公开(公告)日：2005-08-18
申请号：US10777991
申请日：2004-02-12
申请人： MD Abidur Rahman , William Grose , Brett Smith
发明人： MD Abidur Rahman , William Grose , Brett Smith
IPC分类号： H03B1/00 , H03K17/0412
CPC分类号： H03K17/04123
摘要： The present invention provides a system (200) for controlling drive signal timing parameters of an output driver circuit (206). The present invention defines a driver circuit having an output interface (204), and a first transistor (222) coupled to a first voltage supply (230), a first control signal (232), and a first node (220). The circuit also has a first resistive element, coupled between the first node and a second node (234). A second resistive element (228) is coupled to ground. A second transistor (224) is coupled to the second node, to a second control signal (236), and the second resistive element. The circuit has a third transistor (244), coupled to the first and second nodes, and to a third node (240). A third resistive element (242) is coupled between the third node and the output interface. A fourth transistor (238) is coupled to the first and third nodes, and to the output interface. The circuit also has a fifth transistor (216), coupled to a second voltage supply (218), to the first node, and to the output interface.
摘要翻译：本发明提供一种用于控制输出驱动电路（206）的驱动信号定时参数的系统（200）。本发明定义了具有输出接口（204）和耦合到第一电压源（230），第一控制信号（232）和第一节点（220）的第一晶体管（222）的驱动器电路。电路还具有耦合在第一节点和第二节点（234）之间的第一电阻元件。第二电阻元件（228）耦合到地。第二晶体管（224）耦合到第二节点，耦合到第二控制信号（236）和第二电阻元件。电路具有耦合到第一和第二节点以及耦合到第三节点（240）的第三晶体管（244）。第三电阻元件（242）耦合在第三节点和输出接口之间。第四晶体管（238）耦合到第一和第三节点以及输出接口。电路还具有耦合到第二电压源（218）的第五晶体管（216）到第一节点和输出接口。

74. 发明申请

US20050062633A1 METHOD FOR MATCHING RISE AND FALL TIMES OF DRIVE SIGNALS IN A DIGITAL TO ANALOG CONVERTER 有权
标题翻译：用于匹配数字到模拟转换器的驱动信号的上升和下降时间的方法
公开(公告)号：US20050062633A1
公开(公告)日：2005-03-24
申请号：US10975102
申请日：2004-10-28
申请人： Hongwei Wang
发明人： Hongwei Wang
IPC分类号： H03K17/041 , H03K17/0412 , H03M1/66
CPC分类号： H03K17/04106 , H03K17/04123
摘要： A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has a driver portion that generates drive signals based on received respective digital input signals. The drive signals are received at respective switches in the analog section. The driver portion includes logic gates that are used to generate the drive signals, such that a rise and fall time of complementary pairs of drive signals are substantially equal. The driver portion can optionally include an acceleration system to accelerate the rise and fall times of the drive signals. The switches generate respective analog signals from the drive signals.
摘要翻译：系统（例如，数模转换器（DAC））包括数字部分和模拟部分。数字部分具有基于接收的相应数字输入信号产生驱动信号的驱动器部分。在模拟部分的相应开关处接收驱动信号。驱动器部分包括用于产生驱动信号的逻辑门，使得互补驱动信号对的上升和下降时间基本相等。驱动器部分可以可选地包括加速系统以加速驱动信号的上升和下降时间。开关从驱动信号产生相应的模拟信号。

75. 发明授权

US06861892B1 Load-generated drive, substantially no quiescent current, techniques and circuits for high speed switching of transistors 有权
标题翻译：负载产生的驱动器，基本上没有静态电流，用于晶体管高速切换的技术和电路
公开(公告)号：US06861892B1
公开(公告)日：2005-03-01
申请号：US10350552
申请日：2003-01-22
申请人： Karl Edwards
发明人： Karl Edwards
IPC分类号： H03K17/0412 , H03K17/042 , H03K17/06 , H03K17/04
CPC分类号： H03K17/04213 , H03K17/04126 , H03K17/06
摘要： Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.
摘要翻译：提供了用于晶体管高速切换的技术和电路。这些技术和电路在输出设备的输出电流成比例地改变输出设备的驱动电流的同时切换输出设备。此外，这些技术和电路提供基本上没有静态电流的开关电路。这是通过对由输出设备传导的输出电流进行采样并使用样本作为信号来驱动输出设备完全打开或将输出设备完全关断来实现的。

76. 发明授权

US06858895B2 Circuit configuration having a field-effect transistor operable at higher frequencies 有权
标题翻译：具有可在较高频率下工作的场效应晶体管的电路配置
公开(公告)号：US06858895B2
公开(公告)日：2005-02-22
申请号：US10390870
申请日：2003-03-17
申请人： Martin Feldtkeller , Walter Rieger , Wolfgang Friesacher
发明人： Martin Feldtkeller , Walter Rieger , Wolfgang Friesacher
IPC分类号： H01L29/423 , H01L29/78 , H03K17/0412 , H03K17/16 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/7815 , H01L29/7831 , H03K17/04123 , H03K17/162
摘要： A circuit configuration for the switch-on/off control of a DMOS power transistor has at least one first gate electrode and, separate from the latter, a second gate electrode, which are capacitively coupled to one another by a capacitance distributed over the field-effect transistor and which can be driven via separate external gate electrode terminals. The circuit configuration has two individual driver circuits and a generating circuit in order to feed a first drive signal to the first gate electrode and a second drive signal to the second gate electrode, the second drive signal being delayed with respect to the first drive signal.
摘要翻译：用于DMOS功率晶体管的接通/断开控制的电路配置具有至少一个第一栅极电极，并且与后者分开第二栅电极，第二栅电极通过分布在场效应晶体管上的电容彼此电容耦合，并且可以通过单独的外部栅电极端子来驱动。该电路配置具有两个单独的驱动电路和一个产生电路，以便将第一驱动信号馈送到第一栅电极，并将第二驱动信号馈送到第二栅电极，第二驱动信号相对于第一驱动信号被延迟。

77. 发明申请

US20050037725A1 Shaping the drive signal of a mixing device 失效
标题翻译：整形搅拌装置的驱动信号
公开(公告)号：US20050037725A1
公开(公告)日：2005-02-17
申请号：US10639177
申请日：2003-08-11
申请人： Michael Vice
发明人： Michael Vice
IPC分类号： H03K7/06 , H03K17/0412 , H03K17/06 , H04B1/10
CPC分类号： H03K17/063 , H03K7/06 , H03K17/04123
摘要： Techniques for shaping the drive signal of a mixing device to overcome a characteristic capacitance of the control terminal of the mixing device and reduce the time the mixing device is in an intermediate state between its on and off states.
摘要翻译：用于对混合装置的驱动信号进行整形以克服混合装置的控制端子的特性电容并减少混合装置在其打开和关闭状态之间处于中间状态的时间的技术。

78. 发明授权

US6064327A Constant voltage generation circuit 失效
标题翻译：恒压发电电路
公开(公告)号：US6064327A
公开(公告)日：2000-05-16
申请号：US6902
申请日：1998-01-14
申请人： Fumihiro Ryoho , Taiki Nishiuchi , Terunori Kubo
发明人： Fumihiro Ryoho , Taiki Nishiuchi , Terunori Kubo
IPC分类号： H03M1/66 , H03K17/00 , H03K17/0412 , H03K17/16 , H03M1/76 , H03M1/78
CPC分类号： H03K17/005 , H03K17/04123 , H03K17/164
摘要： A constant voltage generation circuit in which a charging circuit (T1) connected to one side of resistors (LR2 to LR5) rapidly supplies a higher voltage, that is further higher than any voltage generated at each of the resistors (LR2 to LR5), to the output terminal (OT) during a desired time period when one of switches (SW2 to SW4) turns on to provide the voltage to be switched to the output terminal (OT) and when the voltage to be switched is higher than a current voltage of the output terminal (OT). Furthermore, in the circuit, a charging circuit (T2 ) connected to other side of resistors (LR2 to LR5) rapidly supplies a lower voltage, that is further lower than any voltage generated at each of the resistors (LR2 to LR5), to the output terminal (OT) during a desired time period when one of switches (SW2 to SW4) turns on to provide the voltage to be switched to the output terminal (OT) and when the voltage to be switched is lower than a current voltage of the output terminal (OT).
摘要翻译：连接到电阻器（LR2〜LR5）的一侧的充电电路（T1）的电压快速地提供比电阻器（LR2〜LR5）中的每一个产生的任何电压更高的电压，在开关（SW2〜SW4）中的一个导通以提供要切换到输出端子（OT）的电压的期望时间段期间的输出端子（OT），并且当要切换的电压高于当前电压输出端（OT）。此外，在电路中，连接到电阻器（LR2〜LR5）的另一侧的充电电路（T2）快速地将比在电阻器（LR2〜LR5）中的每一个产生的任何电压更低的电压提供给输出端子（OT）在期望的时间段期间，当开关（SW2至SW4）中的一个导通以提供要切换到输出端子（OT）的电压时，并且当要切换的电压低于输出端子（OT）。

79. 发明授权

US5990710A High performance write driver for magnetic inductive recording head 失效
标题翻译：磁性感应记录头的高性能写入驱动器
公开(公告)号：US5990710A
公开(公告)日：1999-11-23
申请号：US867097
申请日：1997-06-02
申请人： Tuan V. Ngo , Raymond E. Barnett
发明人： Tuan V. Ngo , Raymond E. Barnett
IPC分类号： G11B5/02 , G11B5/09 , H03F3/45 , H03K17/0412 , H03K17/66 , H03B1/00
CPC分类号： G11B5/022 , G11B5/02 , H03F3/45085 , H03K17/04126 , H03K17/661 , G11B5/09
摘要： A circuit is provided to switch a drive transistor in a write driver circuit controlled by a write control signal to direct write current in a selected direction through an inductive head. Current is selectively conducted from a control region of the drive transistor in response to switching of the write control signal. A first bias circuit limits voltage fluctuation at the control region of the drive transistor. A second bias circuit prevents saturation of the drive transistor.
摘要翻译：提供电路来切换由写入控制信号控制的写入驱动器电路中的驱动晶体管，以通过感应头直接写入指向所选方向的电流。响应于写入控制信号的切换，电流从驱动晶体管的控制区选择性地导通。第一偏置电路限制驱动晶体管的控制区域处的电压波动。第二偏置电路防止驱动晶体管的饱和。

80. 发明授权

US5793226A Data output buffer for multiple power supplies 失效
标题翻译：用于多个电源的数据输出缓冲器
公开(公告)号：US5793226A
公开(公告)日：1998-08-11
申请号：US697088
申请日：1996-08-19
申请人： Hee-Choul Park , Kook-Hwan Kwon
发明人： Hee-Choul Park , Kook-Hwan Kwon
IPC分类号： H01L21/8238 , G11C11/409 , H01L27/092 , H03K17/0412 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/0013 , H03K17/04123
摘要： A data output buffer circuit for a semiconductor memory device operates with two separate power supplies and prevents malfunctions caused by the sequence in which the power supplies are energized. At lease one discharge transistor is used to remove charge from the gate of one or more NMOS push-pull transistors in an output buffer which can be floating in a charged state if one of the power supplies is energized before the other. In one embodiment, the gates of two discharge transistors are cross-coupled to the gates of the push-pull transistors to assure that at least one of the push-pull transistors are turned off. In an alternative embodiment, one or more discharge transistors are connected to the gates of at least one push-pull transistor and are controlled by a pulse generator that generates a pulse signal in response to variations in the voltage of the power supply for the push-pull transistors. In another alternative embodiment, the push-pull buffer includes a PMOS push transistor and an NMOS pull transistor. An inverter, which is powered by the same power supply as the push-pull buffer, drives the gate of the PMOS transistor. Two discharge transistors are connected to the gates of the push-pull transistors, and the gates of the two discharge transistors are cross-coupled to the gate of the NMOS pull transistor and the input of the inverter to assure that at least one of the push-pull transistors are turned off.
摘要翻译：用于半导体存储器件的数据输出缓冲器电路用两个独立的电源工作，并且防止由电源通电的顺序引起的故障。至少一个放电晶体管用于从输出缓冲器中的一个或多个NMOS推挽晶体管的栅极去除电荷，如果其中一个电源在另一个之前通电，则可以将其浮置在充电状态。在一个实施例中，两个放电晶体管的栅极交叉耦合到推挽晶体管的栅极，以确保至少一个推挽晶体管截止。在替代实施例中，一个或多个放电晶体管连接到至少一个推挽晶体管的栅极，并且由脉冲发生器控制，脉冲发生器响应于用于推挽晶体管的电源的电压变化而产生脉冲信号，拉晶体管。在另一替代实施例中，推挽缓冲器包括PMOS推挽晶体管和NMOS拉晶体管。由与推挽式缓冲器相同的电源供电的逆变器驱动PMOS晶体管的栅极。两个放电晶体管连接到推挽晶体管的栅极，并且两个放电晶体管的栅极交叉耦合到NMOS拉晶体管的栅极和反相器的输入端，以确保至少一个推压 - 关闭晶体管。

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