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71. 发明授权

US09862595B2 Method for manufacturing thin-film support beam 有权
公开(公告)号：US09862595B2
公开(公告)日：2018-01-09
申请号：US15023057
申请日：2014-12-04
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Errong Jing
IPC分类号： H01L21/30 , H01L21/46 , B81C1/00
CPC分类号： B81C1/00142 , B81C2201/0108 , B81C2201/0109 , B81C2201/013
摘要： A method for manufacturing a film support beam includes: providing a substrate having opposed first and second surfaces; coating a sacrificial layer on the first surface of the substrate, and patterning the sacrificial layer; depositing a dielectric film on the sacrificial layer to form a dielectric film layer, and depositing a metal film on the dielectric film layer to form a metal film layer; patterning the metal film layer, and dividing a patterned area of the metal film layer into a metal film pattern of a support beam portion and a metal film pattern of a non-support beam portion, wherein a width of the metal film pattern of the support beam portion is greater than a width of a final support beam pattern, and a width of the metal film pattern of the non-support beam portion is equal to a width of a width of a final non-support beam pattern at the moment; photoetching and etching on the metal film layer and the dielectric film layer to obtain the final support beam pattern, the final non-support beam pattern and a final dielectric film layer, wherein the final dielectric film layer serves as a support film of the final support beam pattern and the final non-support beam pattern; and removing the sacrificial layer.

72. 发明授权

US09859112B2 Bonded semiconductor structures 有权
公开(公告)号：US09859112B2
公开(公告)日：2018-01-02
申请号：US13945217
申请日：2013-07-18
申请人： Taiwan Semiconductor Manufacturing Co., LTD.
发明人： Jing-Cheng Lin
IPC分类号： H01L21/30 , H01L21/02 , H01L27/06 , H01L21/822 , H01L21/20 , H01L23/48 , H01L21/762
CPC分类号： H01L21/02104 , H01L21/2007 , H01L21/76254 , H01L21/8221 , H01L23/481 , H01L27/0688 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method is disclosed that includes the steps outlined below. An epitaxial layer is formed on a first semiconductor substrate. At least one implant species is implanted between the epitaxial layer and the first semiconductor substrate to form an ion-implanted layer. The epitaxial layer is bonded to a bonding oxide layer of a second semiconductor substrate. The first semiconductor substrate is separated from the ion-implanted layer.

73. 发明授权

US09852944B2 Backside contact to a final substrate 有权
公开(公告)号：US09852944B2
公开(公告)日：2017-12-26
申请号：US15274406
申请日：2016-09-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeffrey P. Gambino , Mark D. Jaffe , Steven M. Shank , Anthony K. Stamper
IPC分类号： H01L21/30 , H01L21/768 , H01L23/482 , H01L21/762 , H01L23/532 , H01L27/12 , H01L29/06 , H01L29/10 , H01L21/683 , H01L21/74
CPC分类号： H01L21/76895 , H01L21/6835 , H01L21/743 , H01L21/76251 , H01L21/76898 , H01L23/4825 , H01L23/4827 , H01L23/53271 , H01L27/1203 , H01L29/0649 , H01L29/1087 , H01L2221/68327 , H01L2221/6834 , H01L2221/68368
摘要： Device structures and fabrication methods for a backside contact to a final substrate. An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.

74. 发明授权

US09847325B2 Electronic device 有权
公开(公告)号：US09847325B2
公开(公告)日：2017-12-19
申请号：US15354484
申请日：2016-11-17
申请人： Renesas Electronics Corporation
发明人： Yoichiro Kurita , Masaya Kawano , Koji Soejima
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/00 , H01L21/30 , H01L21/46 , H01L21/4763 , H01L25/00 , H01L21/56 , H01L21/683 , H01L25/18 , H01L23/538 , H01L23/00
CPC分类号： H01L25/50 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L23/522 , H01L23/5226 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/02 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2221/68345 , H01L2221/68372 , H01L2224/02319 , H01L2224/02331 , H01L2224/02333 , H01L2224/02372 , H01L2224/02373 , H01L2224/02379 , H01L2224/02381 , H01L2224/16137 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2225/06513 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/19105 , H05K3/0058 , H05K3/284 , H05K3/4682 , H05K2201/0195 , H05K2201/09527 , H05K2201/096 , H05K2201/09972 , H05K2203/016 , H05K2203/0733 , H05K2203/1469 , H01L2924/00 , H01L2224/0401
摘要： In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

75. 发明授权

US09825017B2 Method for manufacturing semiconductor device 有权
公开(公告)号：US09825017B2
公开(公告)日：2017-11-21
申请号：US15268742
申请日：2016-09-19
申请人： Renesas Electronics Corporation
发明人： Bunji Yasumura , Yoshinori Deguchi , Fumikazu Takei , Akio Hasebe , Naohiro Makihira , Mitsuyuki Kubo
IPC分类号： H01L21/30 , H01L25/00 , H01L23/544 , H01L25/065 , H01L21/683 , H01L25/18 , H01L23/00 , H01L21/66
CPC分类号： H01L25/50 , H01L21/6835 , H01L22/12 , H01L22/14 , H01L23/544 , H01L24/05 , H01L24/06 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2221/68327 , H01L2223/54426 , H01L2223/5448 , H01L2223/54493 , H01L2224/03002 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/06131 , H01L2224/11009 , H01L2224/13025 , H01L2224/13082 , H01L2224/13147 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06593 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/16251 , H01L2924/181 , H01L2224/11 , H01L2924/00
摘要： To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

76. 发明授权

US09822453B2 Substrate processing apparatus, substrate processing method and storage medium storing substrate processing program 有权
公开(公告)号：US09822453B2
公开(公告)日：2017-11-21
申请号：US14560332
申请日：2014-12-04
申请人： Tokyo Electron Limited
发明人： Satoshi Kaneko , Kazuki Motomatsu , Kazunori Sakamoto
IPC分类号： H01L21/30 , H01L21/68 , C25D21/12 , C23C18/16 , H01L21/306
CPC分类号： C23C18/1675 , C23C18/1619 , C23C18/1664 , C25D21/12 , H01L21/306 , H01L21/68
摘要： A substrate entire region treatment process of discharging a processing fluid of a temperature different from a surface temperature of a substrate 3 from a first nozzle 24 toward the substrate is performed while moving the first nozzle toward an outer side from an entire region treatment start position P2 located at a central portion to an entire region treatment end position P5 located at a peripheral portion. Then, after moving the first nozzle toward an inner side to a peripheral region treatment start position P6 located at an outer position than the entire region treatment start position P2, a substrate peripheral region treatment process of discharging the processing fluid from the first nozzle toward the substrate is performed while moving the first nozzle toward the outer side from the peripheral region treatment start position P6 to a peripheral region treatment stop position P7 located at a peripheral portion.

77. 发明授权

US09799695B2 Semiconductor device and method of manufacturing the same, and electronic apparatus 有权
公开(公告)号：US09799695B2
公开(公告)日：2017-10-24
申请号：US15374864
申请日：2016-12-09
申请人： Sony Corporation
发明人： Taku Umebayashi , Hiroshi Takahashi , Reijiroh Shohji
IPC分类号： H01L21/00 , H01L21/46 , H01L21/30 , H01L27/146 , H04N5/225 , H04N5/374
CPC分类号： H01L27/14634 , H01L21/76898 , H01L23/481 , H01L27/14612 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14636 , H01L27/1464 , H01L27/14643 , H01L27/14645 , H01L27/14687 , H01L27/1469 , H01L2224/11 , H04N5/225 , H04N5/374
摘要： A semiconductor device is provided as a back-illuminated solid-state imaging device. The device is manufactured by bonding a first semiconductor wafer with a pixel array in a half-finished product state and a second semiconductor wafer with a logic circuit in a half-finished product state together, making the first semiconductor wafer into a thin film, electrically connecting the pixel array and the logic circuit, making the pixel array and the logic circuit into a finished product state, and dividing the first semiconductor wafer and the second semiconductor being bonded together into microchips.

78. 发明授权

US09793167B2 Method for forming a wafer structure, a method for forming a semiconductor device and a wafer structure 有权
公开(公告)号：US09793167B2
公开(公告)日：2017-10-17
申请号：US15224076
申请日：2016-07-29
申请人： Infineon Technologies AG
发明人： Roland Rupp , Wolfgang Lehnert , Francisco Javier Santos Rodriguez
IPC分类号： H01L21/30 , H01L21/78 , H01L29/16 , H01L21/02
CPC分类号： H01L21/7813 , H01L21/02002 , H01L21/76254 , H01L21/78 , H01L29/1608 , H01L29/861
摘要： A method of producing a semiconductor device and a wafer structure are provided. The method includes attaching a donor wafer comprising silicon carbide to a carrier wafer comprising graphite, splitting the donor wafer along an internal delamination layer so that a split layer comprising silicon carbide and attached to the carrier wafer is formed, removing the carrier wafer above an inner portion of the split layer while leaving a residual portion of the carrier wafer attached to the split layer to form a partially supported wafer, and further processing the partially supported wafer.

79. 发明授权

US09780124B2 Display device including pixel comprising first transistor second transistor and light-emitting element 有权
公开(公告)号：US09780124B2
公开(公告)日：2017-10-03
申请号：US15221642
申请日：2016-07-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Yasuyuki Arai
IPC分类号： H01L27/12 , H01L27/32 , G02F1/1335 , G02F1/1362 , G02F1/1343 , G02F1/1368 , H01L21/02 , H01L21/30 , H01L29/66 , H01L29/786 , G02F1/1333
CPC分类号： H01L27/124 , G02F1/133553 , G02F1/134336 , G02F1/13439 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , G02F2001/136295 , G02F2201/123 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L21/02631 , H01L21/02686 , H01L21/3003 , H01L27/1214 , H01L27/1218 , H01L27/1222 , H01L27/1251 , H01L27/1255 , H01L27/1285 , H01L27/3244 , H01L27/3246 , H01L27/3248 , H01L27/3258 , H01L27/326 , H01L27/3262 , H01L27/3265 , H01L27/3276 , H01L27/3279 , H01L29/66537 , H01L29/78621 , H01L29/78633 , H01L29/78678 , H01L29/78684 , H01L29/78696
摘要： An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

80. 发明授权

US09773694B2 Method for manufacturing bonded wafer 有权
公开(公告)号：US09773694B2
公开(公告)日：2017-09-26
申请号：US15120905
申请日：2015-02-12
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： Norihiro Kobayashi , Hiroji Aga
IPC分类号： H01L21/30 , H01L21/46 , H01L21/762 , H01L27/12 , H01L21/265 , H01L21/324 , H01L21/02
CPC分类号： H01L21/76254 , H01L21/02052 , H01L21/02238 , H01L21/02255 , H01L21/26506 , H01L21/26533 , H01L21/30604 , H01L21/324 , H01L21/3247 , H01L27/12
摘要： A method for manufacturing a bonded wafer, includes: ion-implanting a gas ion such as a hydrogen ion from a surface of a bond wafer, thereby forming an ion-implanted layer; bonding the bond wafer and a base wafer; producing a bonded wafer having a thin-film on the base wafer by delaminating the bond wafer along the ion-implanted layer; and performing an RTA treatment on the bonded wafer in a hydrogen gas-containing atmosphere; wherein a protective film is formed onto the surface of the thin-film in a heat treatment furnace in the course of temperature-falling from the maximum temperature of the RTA treatment before the bonded wafer is taken out from the heat treatment furnace; and then the bonded wafer with the protective film being formed thereon is taken out from the heat treatment furnace, and is then cleaned with a cleaning liquid which can etch the protective film and the thin-film.

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