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71. 发明授权

US09621173B1 Circuits and methods of implementing time-average-frequency direct period synthesizer on programmable logic chip and driving applications using the same 有权
公开(公告)号：US09621173B1
公开(公告)日：2017-04-11
申请号：US14945468
申请日：2015-11-19
申请人： Liming Xiu
发明人： Liming Xiu
IPC分类号： G06F17/50 , H03L7/197 , H03K19/173 , H03K19/017 , H03K19/018 , G06F1/10 , G06F1/12 , H03L7/099 , H03K19/0185 , H03K19/096
CPC分类号： H03L7/197 , G06F1/10 , G06F1/12 , G06F17/5045 , G06F17/505 , G06F17/5054 , H03K19/01728 , H03K19/01855 , H03K19/096 , H03K19/1737 , H03L7/0812 , H03L7/0991 , H03L7/16 , H03L7/18
摘要： Circuits of a TAF-DPS clock generator implemented on programmable logic chip comprise: 1) a base time unit generator created from configurable blocks, or on-chip PLL, or on-chip DLL, said base time unit generator produces a plurality of phase-evenly-spaced-signals; 2) a TAF-DPS frequency synthesizer created by configuring configurable blocks of said programmable logic chip, said TAF-DPS frequency synthesizer takes said plurality of phase-evenly-spaced-signals as its input. Methods of creating flexible clock signal to drive application comprise: 1) selecting one or more strategic areas in said programmable logic chip; 2) creating one or more TAF-DPS clock generator for each said area by using the configurable resource in said area; 3) creating control function to control the frequency and duty-cycle of the TAF-DPS clock generator output, said control function can be circuit created from configuring configurable blocks, said control function can also be achieved by software; 4) driving the circuits in application by the flexible clock generated from said TAF-DPS clock generator.

72. 发明授权

US09391519B2 Low quiescent current pull-down circuit 有权
标题翻译：低静态电流下拉电路
公开(公告)号：US09391519B2
公开(公告)日：2016-07-12
申请号：US14311907
申请日：2014-06-23
申请人： Analog Devices Global
发明人： Danzhu Lu , Xiaohan Gong , Bin Shao
IPC分类号： H03K3/356 , H02M3/158 , H03K19/017
CPC分类号： H02M3/158 , H03K3/356 , H03K19/01721
摘要： A device to detect an electrical signal is provided. The device includes sensing, output, and pull-down nodes. The device includes a pull-down circuit having a native metal-oxide-semiconductor field-effect transistor (MOSFET) to pull down the output node to approximately a voltage of the pull-down node. The device includes a switch circuit having a junction field-effect transistor (JFET). The JFET turns on the pull-down circuit in response to a voltage of the sensing node being less than a first threshold. The JFET also turns off the pull-down circuit in response to the voltage of the sensing node being greater than the first threshold.
摘要翻译：提供了一种用于检测电信号的装置。该设备包括感测，输出和下拉节点。该器件包括具有天然金属氧化物半导体场效应晶体管（MOSFET）的下拉电路，以将输出节点下拉到大约下拉节点的电压。该器件包括具有结型场效应晶体管（JFET）的开关电路。 JFET响应于感测节点的电压小于第一阈值而导通下拉电路。 JFET还响应于感测节点的电压大于第一阈值而关断下拉电路。

73. 发明授权

US09356598B2 Threshold logic gates with resistive networks 有权
标题翻译：具有电阻网络的门限逻辑门
公开(公告)号：US09356598B2
公开(公告)日：2016-05-31
申请号：US14792163
申请日：2015-07-06
申请人： Sarma Vrudhula , Jinghua Yang , Niranjan Kulkarni , Shimeng Yu
发明人： Sarma Vrudhula , Jinghua Yang , Niranjan Kulkarni , Shimeng Yu
IPC分类号： G11C7/06 , H03K19/23 , H03K19/00 , G11C13/00 , G06F17/50 , H03K19/08 , H03K19/017 , H03K19/21 , G11C17/16 , G11C17/18
CPC分类号： H03K19/0013 , G06F17/505 , G06F17/5068 , G06F2217/12 , G11C7/065 , G11C13/0002 , G11C13/003 , G11C13/004 , G11C17/165 , G11C17/18 , G11C2013/0042 , G11C2213/71 , G11C2213/79 , H03K19/0027 , H03K19/01707 , H03K19/0813 , H03K19/215 , Y02P90/265
摘要： This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.
摘要翻译：本公开一般涉及用于集成电路（IC）的阈值逻辑元件。在一个实施例中，阈值逻辑元件具有第一输入门网络，第二输入门网络，差分读出放大器和电阻网络。第一输入门网络被配置为接收第一组逻辑信号，而第二输入门网络被配置为接收第二组逻辑信号。差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分输出。电阻网络耦合在差分读出放大器和第一输入门网络之间以及差分读出放大器与第二输入门网络之间。电阻网络使门限逻辑元件不易受工艺变化的影响。

74. 发明授权

US09214475B2 All N-type transistor inverter circuit 有权
标题翻译：所有N型晶体管逆变电路
公开(公告)号：US09214475B2
公开(公告)日：2015-12-15
申请号：US13937752
申请日：2013-07-09
申请人： Pixtronix, Inc.
发明人： Ilias Pappas
IPC分类号： G09G3/20 , H01L27/12 , G09G3/34 , G11C19/28 , H03K19/0944 , H03K19/017 , H03K19/20
CPC分类号： H01L27/1225 , G09G3/3433 , G09G2310/0267 , G09G2310/0286 , G09G2310/0291 , G09G2330/021 , G11C19/28 , H01L27/1255 , H03K19/01714 , H03K19/09441 , H03K19/20
摘要： This disclosure provides systems, methods and apparatus for an all n-type transistor inverter circuit. A circuit can include an input thin film transistor (TFT), a pull-down TFT, a discharge TFT, a first pull-up TFT, a second pull-up TFT, and a floating capacitor. The circuit also can include first and second low-voltage voltage sources and first and second high-voltage voltage sources. The TFTs, the capacitor, and the voltage sources can be coupled such that an output of the circuit is the logical opposite of an input of the circuit. In some implementations, the circuit can exhibit zero DC current in both logic states and can output voltages substantially equal to the voltage output by the first low-voltage voltage source and the second high-voltage voltage source. In some implementations, the circuit can be used to construct D flip-flops, buffers, and controllers for an active matrix electronic display.
摘要翻译：本公开提供了用于全n型晶体管反相器电路的系统，方法和装置。电路可以包括输入薄膜晶体管（TFT），下拉式TFT，放电TFT，第一上拉TFT，第二上拉TFT和浮动电容器。电路还可以包括第一和第二低压电压源以及第一和第二高压电压源。 TFT，电容器和电压源可以被耦合，使得电路的输出与电路的输入逻辑相反。在一些实施方案中，电路可以在两个逻辑状态下呈现零直流电流，并且可以输出基本上等于由第一低压电压源和第二高压电压源输出的电压的电压。在一些实现中，该电路可用于构建用于有源矩阵电子显示器的D触发器，缓冲器和控制器。

75. 发明授权

US09209174B2 Circuit element including a layer of a stress-creating material providing a variable stress and method for the formation thereof 有权
标题翻译：电路元件包括提供可变应力的应力产生材料层及其形成方法
公开(公告)号：US09209174B2
公开(公告)日：2015-12-08
申请号：US13768275
申请日：2013-02-15
申请人： GLOBALFOUNDRIES Inc.
发明人： Johannes von Kluge
IPC分类号： H01L29/78 , H01L29/66 , H01L27/088 , G05F3/02 , H01L21/66 , H03K19/20 , H01L49/02 , H01L29/8605 , H03K19/017 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/7842 , G05F3/02 , G05F3/262 , H01L21/823807 , H01L22/30 , H01L27/088 , H01L27/092 , H01L28/20 , H01L29/66477 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/78 , H01L29/7833 , H01L29/8605 , H03K19/017 , H03K19/20
摘要： A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable in response to a signal acting on the stress-creating material. The layer of stress-creating material is arranged to provide a stress in at least the channel region. The stress provided in at least the channel region is variable in response to the signal acting on the stress-creating material. Layers of stress-creating material providing a stress that is variable in response to a signal acting on the stress-creating material may also be used in circuit elements other than transistors, for example, resistors.
摘要翻译：晶体管包括源极区，漏极区，沟道区，栅电极和应力产生材料层。应力产生材料提供响应于作用在应力产生材料上的信号而变化的应力。应力产生材料层被布置成在至少沟道区域中产生应力。至少在通道区域中提供的应力响应于作用在应力产生材料上的信号而变化。提供响应于作用在应力产生材料上的信号而变化的应力的应力产生材料层也可用于除了晶体管之外的电路元件，例如电阻器。

76. 发明申请

US20150188541A1 DYNAMICALLY ADJUSTABLE CIRCUIT WITH CIRCUIT OF CHARACTERIZED-PATH AND METHOD FOR GENERATING CIRCUIT OF CHARACTERIZED-PATH 有权
标题翻译：具有特征线的电路的动态可调电路以及用于产生特征路径的电路的方法
公开(公告)号：US20150188541A1
公开(公告)日：2015-07-02
申请号：US14569023
申请日：2014-12-12
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： Kuo-Su HSIAO , Chun-Yuan CHENG , Chi-Tien SUN
IPC分类号： H03K19/00 , H03K19/017 , H03K19/01
CPC分类号： H03K19/0008 , H03K19/01 , H03K19/017
摘要： An integrated circuit and a method are provided. An integrated circuit comprises a first circuit, with a first character and at least one external control signal, and a character control unit. The character control unit controls the at least one external control signal and has a second circuit, with a second character essentially proportional to the first character, a character adjuster for adjusting the at least one external control signal, and a character monitor for monitoring the operation behavior of the second circuit to control the character adjuster to adjust the at least one external control signal accordingly.
摘要翻译：提供集成电路和方法。集成电路包括具有第一字符和至少一个外部控制信号的第一电路和字符控制单元。字符控制单元控制至少一个外部控制信号，并且具有第二电路，第二个字符与第一个字符基本成比例;字符调整器，用于调整至少一个外部控制信号;以及字符监视器，用于监视操作第二电路的行为来控制字符调整器相应地调整至少一个外部控制信号。

77. 发明授权

US09035676B2 Level shifter with low voltage loss 有权
标题翻译：电平移位器具有低电压损耗
公开(公告)号：US09035676B2
公开(公告)日：2015-05-19
申请号：US13689534
申请日：2012-11-29
申请人： Parade Technologies, Ltd.
发明人： Liang Xu , Hongquan Wang
IPC分类号： H03K19/017 , H03K19/094 , H04N5/66 , G09G5/00 , H03K19/0185
CPC分类号： H04N5/66 , G09G5/006 , G09G2310/0289 , G09G2370/047 , G09G2370/10 , G09G2370/12 , H03K19/018507
摘要： A system and method are disclosed for level shifting a DDC bus with a low voltage loss. A pull up circuit includes an NMOS transistor, a PMOS transistor and resistor. An NMOS pull up gate is also included in line with the DDC bus. When powered, the level shifter adjusts the voltage of transmitted signals to match the voltage of a receiving device. The resulting adjusted is slightly lower due to a threshold voltage lost across one or more transistors. Additionally, when unpowered, the level shifter releases the signal transmission line. Unadjusted signals can then be transmitted without consumption of power by the level shifter.
摘要翻译：公开了一种具有低电压损耗的DDC总线电平转换的系统和方法。上拉电路包括NMOS晶体管，PMOS晶体管和电阻器。一个NMOS上拉门也与DDC总线一致。当供电时，电平转换器调节发射信号的电压以匹配接收设备的电压。由于一个或多个晶体管上的阈值电压损失，所调整的结果稍微降低。此外，当无电源时，电平移位器释放信号传输线。然后可以传输未调整的信号，而不会由电平转换器消耗功率。

78. 发明授权

US09024930B2 Pulse output circuit, shift register, and display device 有权
标题翻译：脉冲输出电路，移位寄存器和显示设备
公开(公告)号：US09024930B2
公开(公告)日：2015-05-05
申请号：US11968801
申请日：2008-01-03
申请人： Shou Nagao , Munehiro Azami , Yoshifumi Tanada
发明人： Shou Nagao , Munehiro Azami , Yoshifumi Tanada
IPC分类号： G06F3/038 , G09G5/00 , G09G3/36 , H03K19/096 , G11C19/00 , G11C19/28 , H03K19/017
CPC分类号： G09G3/3648 , G09G3/3614 , G09G3/3688 , G09G2300/0408 , G09G2300/0426 , G09G2310/0254 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/0297 , G09G2310/08 , G11C19/00 , G11C19/28 , H01L2924/0002 , H03K19/01735 , H03K19/096 , H01L2924/00
摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.
摘要翻译：提供一种电路，其由一种导电类型的TFT构成，并且能够输出正常振幅的信号。当输入时钟信号CK1变为高电平时，TFT（101,103）中的每一个导通以将信号输出部分（Out）处的电位置为低电平。然后将脉冲输入到信号输入部（In）并变为高电平。 TFT（102）的栅极电位增加到（VDD-V thN），栅极浮起。 TFT（102）因此被导通。然后，CK1变为低电平，并且每个TFT（101,103）被关断。同时，CK3变为高电平，信号输出部分的电位增加。同时，通过电容器（104）的功能，TFT（102）的栅极处的电位增加到等于或高于（VDD + V thN）的电平，使得出现在信号输出部分（Out ）变为等于VDD。当SP变低时 CK3变低并且CK1变为高电平时，信号输出部（Out）的电位再次变为低电平。

79. 发明授权

US08779850B2 Bootstrap circuit 有权
标题翻译：自举电路
公开(公告)号：US08779850B2
公开(公告)日：2014-07-15
申请号：US13903055
申请日：2013-05-28
申请人： Orise Technology Co., Ltd.
发明人： Che-Wei Wu
IPC分类号： H03K17/16 , H03K3/013 , H03K19/017
CPC分类号： H03K3/013 , H03K19/01735
摘要： A bootstrap circuit includes an input terminal, an inverting input terminal, an output terminal, an inverting output terminal, a first sub-bootstrap circuit, a second sub-bootstrap circuit, and a charging path providing circuit. The first sub-bootstrap circuit includes a first bootstrap capacitor, a first charging path, a first discharging path, and a first high voltage providing path. The charging path providing circuit includes a third charging path. In response to a high voltage level inputted into the input terminal, the first charging path and the third charging path are turned on, the first bootstrap capacitor is charged to a capacitor voltage, and the first discharging path is turned on to discharge the output terminal. In response to a low voltage level inputted into the input terminal, a first superimposed voltage including the high voltage level and the capacitor voltage is provided to the output terminal.
摘要翻译：自举电路包括输入端子，反相输入端子，输出端子，反相输出端子，第一子自举电路，第二子自举电路和充电路径提供电路。第一子自举电路包括第一自举电容器，第一充电路径，第一放电路径和第一高电压提供路径。充电路径提供电路包括第三充电路径。响应于输入到输入端子的高电压电平，第一充电路径和第三充电路径导通，第一自举电容器被充电到电容器电压，并且第一放电路径导通以使输出端子。响应于输入到输入端子的低电压电平，向输出端子提供包括高电压电平和电容器电压的第一叠加电压。

80. 发明申请

US20120274357A1 Reducing Narrow Gate Width Effects in an Integrated Circuit Design 失效
标题翻译：降低集成电路设计中的窄门宽度效应
公开(公告)号：US20120274357A1
公开(公告)日：2012-11-01
申请号：US13097537
申请日：2011-04-29
申请人： Edgardo F. Klass
发明人： Edgardo F. Klass
IPC分类号： H03K19/017 , G06F17/50
CPC分类号： H03K19/00307 , G06F2217/78 , G06F2217/80 , G06F2217/84
摘要： A method for reducing narrow gate width effects in an integrated circuit includes finding the smallest transistor channel widths that are larger than the minimum width for the technology for library cells that produce logic blocks that meet timing constraints while using the least amount of power and have the smallest possible area. The method may include characterizing a device library while varying process, voltage and temperature parameters, and synthesizing an HDL representation of a functional logic block including cells from the device library. The method may also include determining whether timing, area, and power values of the functional logic block are within a predetermined range. In response to the timing, area, and power values not being within the predetermined range, iteratively increasing the channel width of at least a portion of the transistors of at least one of the cells in the device library.
摘要翻译：一种用于减小集成电路中的窄栅极宽度效应的方法包括找到最大的晶体管沟道宽度，该晶体管沟道宽度大于用于在使用最小量的功率时产生符合时序约束的逻辑块的库单元的技术的最小宽度，并且具有尽可能小的区域。该方法可以包括在改变过程，电压和温度参数的同时表征设备库，以及合成包括来自设备库的单元的功能逻辑块的HDL表示。该方法还可以包括确定功能逻辑块的定时，区域和功率值是否在预定范围内。响应于定时，面积和功率值不在预定范围内，迭代地增加设备库中至少一个单元的至少一部分晶体管的沟道宽度。

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