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1. 发明申请

US20180076815A1 VOTING CIRCUITS AND METHODS FOR TRUSTED FAULT TOLERANCE OF A SYSTEM OF UNTRUSTED SUBSYSTEMS 审中-公开
公开(公告)号：US20180076815A1
公开(公告)日：2018-03-15
申请号：US15692024
申请日：2017-08-31
申请人： The Charles Stark Draper Laboratory, Inc.
发明人： Richard L. Vigeant , Antonio E. de la Serna
IPC分类号： H03K19/23 , H03K19/08
CPC分类号： H03K19/23 , G06F11/08 , G06F13/28 , G06F13/32 , G06F21/57 , G06F21/71 , G06F2211/1097 , G07C13/02 , H03K19/0813 , H03K25/02
摘要： Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.

2. 发明授权

US09876503B2 Method of obfuscating digital logic circuits using threshold voltage 有权
公开(公告)号：US09876503B2
公开(公告)日：2018-01-23
申请号：US15390970
申请日：2016-12-27
申请人： Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni , Joseph Davis
发明人： Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni , Joseph Davis
IPC分类号： H03K19/20 , H03K19/08 , H03K19/096 , H03K19/21
CPC分类号： H03K19/0813 , H03K19/0963 , H03K19/21
摘要： A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

3. 发明授权

US09257984B2 Multi-threshold circuitry based on silicon-on-insulator technology 有权
标题翻译：基于绝缘体上硅技术的多阈值电路
公开(公告)号：US09257984B2
公开(公告)日：2016-02-09
申请号：US14487678
申请日：2014-09-16
申请人： Wave Semiconductor, Inc.
发明人： Gajendra Prasad Singh , Roger Carpenter
IPC分类号： H01L27/10 , H03K19/0948 , H01L27/12 , G06F17/50 , H01L21/84 , H03K19/08 , H03K19/20
CPC分类号： H03K19/0948 , G06F17/505 , G06F17/5072 , H01L21/84 , H01L27/1203 , H03K19/0813 , H03K19/20
摘要： Multiple threshold voltage circuitry based on silicon-on-insulator (SOI) technology is disclosed which utilizes N-wells and/or P-wells underneath the insulator in SOI FETs. The well under a FET is biased to influence the threshold voltage of the FET. A PFET and an NFET share a common buried P-well or N-well. Various types of logic can be fabricated in silicon-on-insulator (SOI) technology using multiple threshold voltage FETs. Embodiments provide circuits including the advantageous properties of both low-leakage transistors and high-speed transistors.
摘要翻译：公开了基于绝缘体上硅（SOI）技术的多阈值电压电路，其利用SOI FET中的绝缘体下方的N阱和/或P阱。 FET下的阱被偏置以影响FET的阈值电压。 PFET和NFET共享一个普通的P阱或N阱。可以使用多个阈值电压FET在绝缘体上硅（SOI）技术中制造各种类型的逻辑。实施例提供了包括低泄漏晶体管和高速晶体管的有利特性的电路。

4. 发明申请

US20120133390A1 ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN 失效
标题翻译：超低功耗多路非同步电路设计
公开(公告)号：US20120133390A1
公开(公告)日：2012-05-31
申请号：US13175168
申请日：2011-07-01
申请人： Jia Di , Scott Christopher Smith
发明人： Jia Di , Scott Christopher Smith
IPC分类号： H03K19/23
CPC分类号： H03K19/0016 , H03K19/0813
摘要： A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.
摘要翻译：多阈值CMOS NULL约定逻辑异步电路（MTNCL）。 MTNCL电路提供延迟不敏感的逻辑运算，具有显着的泄漏功率和主动能量减少。 MTNCL电路还能够在极低的电源电压范围内正常工作，直到子阈值区域进一步降低功率。四个MTNCL架构和四个MTNCL阈值门设计为无毛刺，超低功耗和更快的电路提供了异步逻辑设计方法，无需区域开销。

5. 发明申请

US20100321061A1 THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE 有权
标题翻译：具有低泄漏功率和高性能的阈值逻辑元件
公开(公告)号：US20100321061A1
公开(公告)日：2010-12-23
申请号：US12867352
申请日：2009-02-13
申请人： Samuel Leshner , Sarma Vrudhula
发明人： Samuel Leshner , Sarma Vrudhula
IPC分类号： H03K19/23
CPC分类号： H03K19/0813
摘要： Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.
摘要翻译：提供了阈值逻辑元件的实施例。优选地，本文所讨论的阈值逻辑元件的实施例具有低泄漏功率和高性能特性。在优选实施例中，阈值逻辑元件是阈值逻辑锁存器（TLL）。 TLL是一种动态操作的电流模式阈值逻辑单元，可提供快速有效的数字逻辑功能实现。 TLL可以同步或异步操作，并且与标准互补金属氧化物半导体（CMOS）技术完全兼容。

6. 发明授权

US06900658B1 Null convention threshold gate 失效
标题翻译：空常规阈值门
公开(公告)号：US06900658B1
公开(公告)日：2005-05-31
申请号：US08867675
申请日：1997-06-02
申请人： Gerald E. Sobelman , Karl M. Fant
发明人： Gerald E. Sobelman , Karl M. Fant
IPC分类号： G06F7/50 , G06F7/505 , G06F11/08 , H03K19/08 , H03K19/096 , H03K19/23 , H03M5/02 , H03M5/16
CPC分类号： G06F7/5052 , G06F7/502 , G06F11/085 , G06F2207/4822 , H03K19/0813 , H03K19/096 , H03K19/23 , H03M5/02 , H03M5/16
摘要： A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.
摘要翻译： NULL约定阈值门接收多个输入，每个输入具有断言状态和空状态。当有效输入的数量超过阈值数时，阈值门将其输出切换到有效状态。只有在所有输入返回到NULL之后，门槛值将其输出切换到NULL状态。信号状态可以被实现为不同的电流电平。

7. 发明授权

US06430585B1 Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereof 失效
标题翻译：基于耐噪电导的逻辑门及其操作和制造方法
公开(公告)号：US06430585B1
公开(公告)日：2002-08-06
申请号：US09406367
申请日：1999-09-28
申请人： Valeriu Beiu
发明人： Valeriu Beiu
IPC分类号： G06F750
CPC分类号： G06F7/52 , G06F7/5013 , G06F2207/4818 , H03K19/0813
摘要： A logic gate, an adder and methods of operating and manufacturing the same. In one embodiment, the logic gate includes: (1) a summer, having at least two single-bit inputs and a noise-suppression input with corresponding conductances representing discrete weights, that generates a weighted sum of input binary digits presented at the at least two single-bit inputs and the noise-suppression input and (2) a quantizer, coupled to the summer, that generates an output binary digit at a binary output thereof that is a function of the weighted sum, the noise-suppression input increasing a noise tolerance of the logic gate.
摘要翻译：逻辑门，加法器和操作和制造方法。在一个实施例中，逻辑门包括：（1）具有至少两个单位输入的加法器和具有表示离散权重的对应电导的噪声抑制输入，其产生至少呈现在输入二进制数字的加权和两个单位输入和噪声抑制输入，以及（2）耦合到夏季的量化器，其在其二进制输出处产生作为加权和的函数的输出二进制数字，噪声抑制输入增加逻辑门的噪声容限。

8. 发明授权

US06252425B1 Method and apparatus for an N-NARY logic circuit 有权
标题翻译：用于N-NARY逻辑电路的方法和装置
公开(公告)号：US06252425B1
公开(公告)日：2001-06-26
申请号：US09458763
申请日：1999-12-10
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M Petro
IPC分类号： H03K19094
CPC分类号： G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215
摘要： The present invention is a method and apparatus for an N-NARY logic circuit that uses N-NARY signals. The present invention includes a shared logic tree circuit that evaluates one or more N-NARY input signals and produces an N-NARY output signal. The present invention additionally includes a first N-NARY input signal coupled to the shared logic tree circuit and a second N-NARY input signal coupled to the shared logic tree circuit. The shared logic circuit evaluates the first second and second N-NARY input signal and produces an N-NARY output signal coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals, 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.
摘要翻译：本发明是一种使用N-NARY信号的N-NARY逻辑电路的方法和装置。本发明包括共享逻辑树电路，其评估一个或多个N-NARY输入信号并产生N-NARY个输出信号。本发明还包括耦合到共享逻辑树电路的第一N-NARY输入信号和耦合到共享逻辑树电路的第二N-NARY输入信号。共享逻辑电路评估第一第二和第二N-NARY输入信号并产生耦合的N-NARY输出信号，其另外耦合到共享逻辑树电路。本发明使用包括2个N-NARY信号中的1个，3个N-NARY信号中的1个，4个N-NARY信号中的1个，8个N-NARY个信号中的1个，以及N N-NARY个信号的通用信号1的信号。本发明评估包括AND / NAND，OR / NOR或异或/等效函数的任何给定函数。

9. 发明申请

US20010000661A1 Logic circuit utilizing capacitive coupling, an AD converter and a DA converter 失效
标题翻译：使用电容耦合的逻辑电路，AD转换器和DA转换器
公开(公告)号：US20010000661A1
公开(公告)日：2001-05-03
申请号：US09741197
申请日：2000-12-21
申请人： Fujitsu Limited
发明人： Yoshihiro Miyamoto
IPC分类号： H03M005/02
CPC分类号： G06F7/5013 , G06F2207/482 , H03K19/0813 , H03K19/23 , H03M1/129 , H03M1/144 , H03M1/145 , H03M1/403 , H03M1/42 , H03M1/46 , H03M1/60 , H03M1/667 , H03M1/68
摘要： According to the present invention, various logic circuits, AD converters, DA converters and counter circuits can be constituted with a small number of transistors by employing a capacitive coupling circuit. An analog/digital converter comprises: an input terminal, for which analog input is provided; an output terminal of N (N is a plural number) bits, for which binary output is provided; and N unit circuits arranged in parallel, each including an input capacitor having one electrode connected to the input terminal, a first inverter connected to the other electrode of the input capacitor, and a second inverter connected to the first inverter, wherein outputs of the second inverters of the unit circuits are respectively provided for the output terminals, wherein inverted outputs of the outputs for the unit circuits are fed back via feedback capacitors to respective input terminals of the first inverters of the unit circuits corresponding to lower bits, and wherein a capacitance of the feedback capacitor, which corresponds to the inverted output of the M-th (M is an integer) unit circuit from the most significant bit, is nullM times a capacitance of the input capacitor of the unit circuit that is fed back.
摘要翻译：根据本发明，通过采用电容耦合电路，各种逻辑电路，AD转换器，DA转换器和计数器电路可以由少量晶体管构成。一种模拟/数字转换器，包括：输入端，为其提供模拟输入; N（N是多个）位的输出端，提供二进制输出; 和N个单位电路，每个均包括一个输入电容器，该输入电容器具有连接到输入端子的一个电极，连接到输入电容器的另一个电极的第一反相器和连接到第一反相器的第二反相器，其中第二个单元电路的逆变器分别设置用于输出端子，其中用于单位电路的输出的反相输出通过反馈电容器反馈到对应于低位的单元电路的第一反相器的相应输入端子，并且其中电容对应于来自最高有效位的第M（M为整数）单位电路的反相输出的反馈电容是反馈的单位电路的输入电容器的电容的1/2倍。

10. 发明授权

US6046931A Method and apparatus for a RAM circuit having N-nary output interface 有权
标题翻译：具有N个输出接口的RAM电路的方法和装置
公开(公告)号：US6046931A
公开(公告)日：2000-04-04
申请号：US150258
申请日：1998-09-09
申请人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
发明人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21
CPC分类号： H03K19/0813 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G06F7/5443 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-nary, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-nary, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-nary) 1-of-N logic gate.
摘要翻译：具有感测触发器的存储器件，其在耦合到可用时接收地址，并且当感测触发器接收到地址时，将感测触发信号置于感测触发器。存储器件还具有N / N或N输入逻辑门，其提供额外的保证，即当解码地址时不超过一个字线被断言。存储器件还具有N输出或1-N输出驱动器逻辑门，其提供直接用于提供给另一（N-Nary）1-N逻辑门的输出信号。

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