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81. 发明授权

US08214424B2 User level message broadcast mechanism in distributed computing environment 失效
标题翻译：分布式计算环境中的用户级消息广播机制
公开(公告)号：US08214424B2
公开(公告)日：2012-07-03
申请号：US12424837
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Robert S. Blackmore
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Robert S. Blackmore
IPC分类号： G06F15/16
CPC分类号： G06F9/542 , G06F9/546 , G06F11/1443 , G06F2209/546
摘要： A data processing system is programmed to provide a method for enabling user-level one-to-all message/messaging (OTAM) broadcast within a distributed parallel computing environment in which multiple threads of a single job execute on different processing nodes across a network. The method comprises: generating one or more messages for transmission to at least one other processing node accessible via a network, where the messages are generated by/for a first thread executing at the data processing system (first processing node) and the other processing node executes one or more second threads of a same parallel job as the first thread. An OTAM broadcast is transmitting via a host fabric interface (HFI) of the data processing system as a one-to-all broadcast on the network, whereby the messages are transmitted to a cluster of processing nodes across the network that execute threads of the same parallel job as the first thread.
摘要翻译：数据处理系统被编程为提供一种在分布式并行计算环境中实现用户级一对一消息/消息传递（OTAM）广播的方法，其中单个作业的多个线程在跨越网络的不同处理节点上执行。该方法包括：生成一个或多个消息以便传输到经由网络可访问的至少一个其他处理节点，其中消息由数据处理系统（第一处理节点）执行的第一个线程生成，另一个处理节点执行与第一线程相同的并行作业的一个或多个第二线程。 OTAM广播通过数据处理系统的主机结构接口（HFI）作为网络上的一对一广播进行发送，由此将消息传送到跨网络的处理节点群集，该群集执行相同的线程并行作为第一个线程。

82. 发明授权

US08108876B2 Modifying an operation of one or more processors executing message passing interface tasks 失效
标题翻译：修改执行消息传递接口任务的一个或多个处理器的操作
公开(公告)号：US08108876B2
公开(公告)日：2012-01-31
申请号：US11846101
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： G06F9/505 , G06F9/5038 , G06F9/52 , G06F9/522 , G06F9/546 , G06F2209/5019 , G06F2209/5022 , G06F2209/508 , G06F2209/509
摘要： Mechanisms for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing work loads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI Load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了修改执行消息传递接口（MPI）任务的一个或多个处理器的操作的机制。提供了调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待周期。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

83. 发明授权

US08024527B2 Partial cache line accesses based on memory access patterns 有权
标题翻译：基于内存访问模式的部分缓存行访问
公开(公告)号：US08024527B2
公开(公告)日：2011-09-20
申请号：US12024432
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/04
CPC分类号： G06F9/30043 , G06F9/383 , G06F12/0811 , G06F12/0831 , G06F12/0886
摘要： According to a method of data processing in a multiprocessor data processing system, in response to a processor request to read a target granule of a target cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial read request that requests permission to read only the target granule of the target cache line. In response to a combined response to the partial read request indicating success, the combined response representing a system-wide response to the partial read request, the processing unit receives the target granule of the target cache line, supplies the target granule to a requesting processor core, and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the target cache line.
摘要翻译：根据多处理器数据处理系统中的数据处理方法，响应于读取包含多个粒度的目标高速缓存行数据的目标颗粒的处理器请求，处理单元来源于多处理器数据处理系统a的互连部分读取请求，请求权限只读取目标缓存行的目标颗粒。响应于表示成功的部分读取请求的组合响应，表示对部分读取请求的系统范围响应的组合响应，处理单元接收目标高速缓存行的目标颗粒，将目标颗粒提供给请求处理器并且在保持目标高速缓存行的至少一个其他粒子的一致性状态的同时更新目标粒子的相关性状态。

84. 发明授权

US08014387B2 Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture 失效
标题翻译：在多层全图互连架构的超节点中提供完全无阻塞的交换机
公开(公告)号：US08014387B2
公开(公告)日：2011-09-06
申请号：US11845211
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： H04L12/66
CPC分类号： G06F9/5061 , G06F15/17356 , G06F2209/5012 , H04L49/15 , H04L49/25
摘要： A mechanism is provided for transmitting data from a first processor of a data processing system to a second processor of the data processing system. In one or more switches, a set of virtual channels is created, the one or more switches comprising, for each processor, a corresponding switch in the one or more switches. The data is transmitted from the first processor to the second processor through a path comprising a subset of processors of a set of processors in the data processing system. In each processor of the subset of processors, the data is stored in a virtual channel of a corresponding switch before transmitting the data to a next processor. The virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted.
摘要翻译：提供了一种用于将数据从数据处理系统的第一处理器传送到数据处理系统的第二处理器的机构。在一个或多个交换机中，创建一组虚拟通道，一个或多个交换机为每个处理器包括一个或多个交换机中的相应开关。数据通过包括数据处理系统中的一组处理器的处理器的子集的路径从第一处理器传送到第二处理器。在处理器子集的每个处理器中，在将数据发送到下一个处理器之前，将数据存储在相应开关的虚拟通道中。其中存储数据的相应交换机的虚拟通道对应于处理器在数据发送的路径中的位置。

85. 发明授权

US07769892B2 System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architecture 有权
标题翻译：用于处理多层全图互连架构的超节点之间的信息的间接路由的系统和方法
公开(公告)号：US07769892B2
公开(公告)日：2010-08-03
申请号：US11845221
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： H04L12/56 , G06F21/00
CPC分类号： H04L45/00 , H04L45/22
摘要： A method, computer program product, and system are provided for selecting, from a plurality of routes through the data processing system, an indirect route for transmitting data. Data that includes address information is received at a first processor that is to be transmitted to a destination processor. Using routing table data structures, indirect route entries are identified that correspond to indirect routes for transmitting data. An accessed priority table data structure comprises a priority entry for each entry in the routing table data structures. The priority entry specifies a priority of a corresponding entry in the routing table data structures. An indirect route entry is selected that corresponds to an indirect route from the routing table data structures, based on specified priorities. Then the data is transmitted from the first processor to the destination processor using a path corresponding to the selected indirect route entry.
摘要翻译：提供了一种方法，计算机程序产品和系统，用于从通过数据处理系统的多条路线中选择用于发送数据的间接路由。在要发送到目的地处理器的第一处理器处接收包括地址信息的数据。使用路由表数据结构，识别对应于用于传输数据的间接路由的间接路由条目。访问的优先级表数据结构包括路由表数据结构中的每个条目的优先级项。优先级条目指定路由表数据结构中相应条目的优先级。基于指定的优先级，选择对应于来自路由表数据结构的间接路由的间接路由条目。然后使用对应于所选择的间接路由条目的路径从第一处理器将数据发送到目的地处理器。

86. 发明授权

US07769891B2 System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architecture 有权
标题翻译：用于在多层全图互连架构的超节点之间提供多个冗余直接路由的系统和方法
公开(公告)号：US07769891B2
公开(公告)日：2010-08-03
申请号：US11845217
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： H04L12/56 , G06F21/00
CPC分类号： G06F15/17381 , H04L67/327
摘要： A method, computer program product, and system are provided for selecting, from a plurality of routes through the data processing system, a direct route for transmitting data. Data that includes address information is received at a first processor that is to be transmitted to a destination processor. Using routing table data structures, direct route entries are identified that correspond to direct routes for transmitting data. An accessed priority table data structure comprises a priority entry for each entry in the routing table data structures. The priority entry specifies a priority of a corresponding entry in the routing table data structures. A direct route entry is selected that corresponds to a direct route from the routing table data structures, based on specified priorities. Then the data is transmitted from the first processor to the destination processor using a path corresponding to the selected direct route entry.
摘要翻译：提供一种方法，计算机程序产品和系统，用于从数据处理系统的多条路线中选择用于发送数据的直接路由。在要发送到目的地处理器的第一处理器处接收包括地址信息的数据。使用路由表数据结构，识别与发送数据的直接路由相对应的直接路由条目。访问的优先级表数据结构包括路由表数据结构中的每个条目的优先级项。优先级条目指定路由表数据结构中相应条目的优先级。基于指定的优先级，从路由表数据结构中选择对应于直接路由的直接路由条目。然后使用与所选择的直接路由条目相对应的路径，将数据从第一处理器发送到目的地处理器。

87. 发明申请

US20100070712A1 Techniques for Cache Injection in a Processor System with Replacement Policy Position Modification 失效
标题翻译：具有更换政策位置修改的处理器系统中缓存注入的技术
公开(公告)号：US20100070712A1
公开(公告)日：2010-03-18
申请号：US12212977
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0862 , G06F12/0835 , G06F12/127 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).
摘要翻译：用于执行高速缓存注入的技术包括在缓存上监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。然后修改数据块的替换策略位置（以增加数据块在从高速缓存弹出之前消耗的概率）。

88. 发明申请

US20100070710A1 Techniques for Cache Injection in a Processor System 有权
标题翻译：处理器系统中缓存注入的技术
公开(公告)号：US20100070710A1
公开(公告)日：2010-03-18
申请号：US12212917
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F12/00 , G06F13/28
CPC分类号： G06F13/28 , G06F12/0835 , G06F2212/507 , G06F2212/621
摘要： A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：执行高速缓存注入的技术包括监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

89. 发明申请

US20090199209A1 Mechanism for Guaranteeing Delivery of Multi-Packet GSM Message 失效
标题翻译：保证多分组GSM消息传递的机制
公开(公告)号：US20090199209A1
公开(公告)日：2009-08-06
申请号：US12024678
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F3/00
CPC分类号： H04L1/1642 , G06F9/542
摘要： A target task ensures complete delivery of a global shared memory (GSM) message from an originating task to the target task. The target task's HFI receives a first of multiple GSM packets generated from a single GSM message sent from the originating task. The HFI logic assigns a sequence number and corresponding tuple to track receipt of the complete GSM message. The sequence number is unique relative to other sequence numbers assigned to GSM messages that have not been completely received from the initiating task. The HFI updates a count value within the tuple, which comprises the sequence number and the count value for the first GSM packet and for each subsequent GSM packet received for the GSM message. The HFI determines when receipt of the GSM message is complete by comparing the count value with a count total retrieved from the packet header.
摘要翻译：目标任务确保从始发任务到目标任务的全局共享存储器（GSM）消息的完全传递。目标任务的HFI接收从发起任务发送的单个GSM消息产生的多个GSM分组中的第一个。 HFI逻辑分配序列号和对应的元组来跟踪完整GSM消息的接收。相对于分配给尚未完全从发起任务接收的GSM消息的其他序列号，序列号是唯一的。 HFI更新元组内的计数值，其包括第一GSM分组的序列号和计数值以及为GSM消息接收的每个后续GSM分组。通过将计数值与从分组报头检索的计数总数进行比较，HFI确定接收到GSM消息的完成。

90. 发明申请

US20090199194A1 Mechanism to Prevent Illegal Access to Task Address Space by Unauthorized Tasks 有权
标题翻译：通过未经授权的任务防止非法访问任务地址空间的机制
公开(公告)号：US20090199194A1
公开(公告)日：2009-08-06
申请号：US12024410
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F9/50
CPC分类号： G06F9/544 , G06F9/468
摘要： A method and data processing system for tracking global shared memory (GSM) operations to and from a local node configured with a host fabric interface (HFI) coupled to a network fabric. During task/job initialization, the system OS assigns HFI window(s) to handle the GSM packet generation and GSM packet receipt and processing for each local task. HFI processing logic automatically tags each GSM packet generated by the HFI window with a global job identifier (ID) of the job to which the local task is affiliated. The job ID is embedded within each GSM packet placed on the network fabric. On receipt of a GSM packet from the network fabric, the HFI logic retrieves the embedded job ID and compares the embedded job ID with the ID within the HFI window(s). GSM packets are forwarded to an HFI window only when the embedded job ID matches the HFI window's job ID.
摘要翻译：一种用于跟踪与配置有耦合到网络结构的主机结构接口（HFI）的本地节点的全局共享存储器（GSM）操作的方法和数据处理系统。在任务/作业初始化期间，系统OS分配HFI窗口来处理每个本地任务的GSM分组生成和GSM分组接收和处理。 HFI处理逻辑自动将由HFI窗口生成的每个GSM分组标记为本地任务附属于该作业的全局作业标识符（ID）。作业ID被嵌入到放置在网络结构上的每个GSM分组内。在从网络结构接收到GSM分组时，HFI逻辑检索嵌入的作业ID，并将嵌入的作业ID与HFI窗口内的ID进行比较。仅当嵌入的作业ID与HFI窗口的作业ID匹配时，才将GSM数据包转发到HFI窗口。

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