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1. 发明授权

US07996564B2 Remote asynchronous data mover 失效
标题翻译：远程异步数据移动器
公开(公告)号：US07996564B2
公开(公告)日：2011-08-09
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译：分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问数据中心为远程存储器的节点ID。

2. 发明申请

US20100268788A1 Remote Asynchronous Data Mover 失效
标题翻译：远程异步数据移动器
公开(公告)号：US20100268788A1
公开(公告)日：2010-10-21
申请号：US12425093
申请日：2009-04-16
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ronald N. Kalla , Ramakrishnan Rajamony , Balaram Sinharoy , William E. Speight , William J. Starke
IPC分类号： G06F15/167 , G06F9/46 , G06F12/00 , G06F12/10
CPC分类号： G06F9/54 , G06F12/10 , G06F12/1081
摘要： A distributed data processing system executes multiple tasks within a parallel job, including a first local task on a local node and at least one task executing on a remote node, with a remote memory having real address (RA) locations mapped to one or more of the source effective addresses (EA) and destination EA of a data move operation initiated by a task executing on the local node. On initiation of the data move operation, remote asynchronous data move (RADM) logic identifies that the operation moves data to/from a first EA that is memory mapped to an RA of the remote memory. The local processor/RADM logic initiates a RADM operation that moves a copy of the data directly from/to the first remote memory by completing the RADM operation using the network interface cards (NICs) of the source and destination processing nodes, determined by accessing a data center for the node IDs of remote memory.
摘要翻译：分布式数据处理系统在并行作业中执行多个任务，包括本地节点上的第一本地任务和在远程节点上执行的至少一个任务，具有映射到以下的一个或多个的实地址（RA）位置的远程存储器由本地节点上执行的任务启动的数据移动操作的源有效地址（EA）和目标EA。在启动数据移动操作时，远程异步数据移动（RADM）逻辑识别该操作将数据移动到/从第一个EA，该第一个EA是映射到远程存储器的RA的存储器。本地处理器/ RADM逻辑启动RADM操作，其通过使用源和目的地处理节点的网络接口卡（NIC）完成RADM操作，直接从/向第一远程存储器移动数据的副本，其通过访问数据中心为远程存储器的节点ID。

3. 发明申请

US20100070717A1 Techniques for Cache Injection in a Processor System Responsive to a Specific Instruction Sequence 失效
标题翻译：针对特定指令序列的处理器系统中缓存注入的技术
公开(公告)号：US20100070717A1
公开(公告)日：2010-03-18
申请号：US12212961
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/0897 , G06F2212/6024
摘要： A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：用于执行高速缓存注入的技术包括监视特定指令序列的指令流。响应于检测到特定指令序列确定的次数，在总线上的地址被监视在高速缓存。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。

4. 发明授权

US09110885B2 Techniques for cache injection in a processor system 有权
标题翻译：在处理器系统中缓存注入的技术
公开(公告)号：US09110885B2
公开(公告)日：2015-08-18
申请号：US12212917
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F13/28 , G06F12/08
CPC分类号： G06F13/28 , G06F12/0835 , G06F2212/507 , G06F2212/621
摘要： A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：执行高速缓存注入的技术包括监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

5. 发明申请

US20100070711A1 Techniques for Cache Injection in a Processor System Using a Cache Injection Instruction 有权
标题翻译：使用缓存注入指令的处理器系统中缓存注入的技术
公开(公告)号：US20100070711A1
公开(公告)日：2010-03-18
申请号：US12212935
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0862 , G06F3/0604 , G06F3/061 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0835 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.
摘要翻译：用于执行高速缓存注入的技术包括响应于高速缓存注入指令监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于与高速缓存注入指令相关联的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

6. 发明申请

US20100070712A1 Techniques for Cache Injection in a Processor System with Replacement Policy Position Modification 失效
标题翻译：具有更换政策位置修改的处理器系统中缓存注入的技术
公开(公告)号：US20100070712A1
公开(公告)日：2010-03-18
申请号：US12212977
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F12/0862 , G06F12/0835 , G06F12/127 , G06F2212/6028
摘要： A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).
摘要翻译：用于执行高速缓存注入的技术包括在缓存上监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。然后修改数据块的替换策略位置（以增加数据块在从高速缓存弹出之前消耗的概率）。

7. 发明申请

US20100070710A1 Techniques for Cache Injection in a Processor System 有权
标题翻译：处理器系统中缓存注入的技术
公开(公告)号：US20100070710A1
公开(公告)日：2010-03-18
申请号：US12212917
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F12/00 , G06F13/28
CPC分类号： G06F13/28 , G06F12/0835 , G06F2212/507 , G06F2212/621
摘要： A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：执行高速缓存注入的技术包括监视总线上的地址。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，通过高速缓存获取总线上的输入/输出数据的所有权。

8. 发明授权

US08312464B2 Hardware based dynamic load balancing of message passing interface tasks by modifying tasks 失效
标题翻译：基于硬件的动态负载平衡消息传递接口任务通过修改任务
公开(公告)号：US08312464B2
公开(公告)日：2012-11-13
申请号：US11846168
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/5083 , G06F9/522
摘要： Mechanisms are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了通过修改任务来提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢处理器转移到一个或多个较快处理器。

9. 发明授权

US08108619B2 Cache management for partial cache line operations 有权
标题翻译：部分缓存行操作的缓存管理
公开(公告)号：US08108619B2
公开(公告)日：2012-01-31
申请号：US12024447
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/0837 , G06F12/0886
摘要： A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache entries, a plurality of line coherency state fields indicates an associated coherency state applicable to two or more data granules. For at least a particular cache line among the plurality of cache lines, a granule coherency state field indicates a coherency state for a particular granule of the multiple data granules in the particular cache line, where the coherency state field indicated by the granule coherency state field differs from that indicated for the particular cache line by its line coherency state field.
摘要翻译：高速缓冲存储器中的数据处理方法包括：高速缓存阵列中的相应多个条目中的多条高速缓存行数据缓存，其中多个高速缓存行中的每一条包括多个数据粒子。对于多个高速缓存条目中的每一个，多个行相关性状态字段指示适用于两个或更多个数据粒子的相关联的一致性状态。对于多个高速缓存行中的至少一个特定高速缓存行，颗粒一致性状态字段指示特定高速缓存行中的多个数据颗粒的特定颗粒的一致性状态，其中由颗粒一致性状态字段指示的一致性状态字段与特定高速缓存行通过其行一致性状态字段指示的不同。

10. 发明授权

US07958182B2 Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture 失效
标题翻译：在多层全图互连架构中提供集体操作的完整硬件支持
公开(公告)号：US07958182B2
公开(公告)日：2011-06-07
申请号：US11845223
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F15/16
CPC分类号： G06F15/17381
摘要： A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译：提供了一种用于执行集体操作的机制。在第一处理器书中的母处理器的硬件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包括母处理器和其他处理器。在母处理器的硬件中，多个处理器在逻辑上被布置为分层结构中的多个节点。基于层次结构将集体操作发送到多个处理器。在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。

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