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81. 发明授权

US08673701B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08673701B2
公开(公告)日：2014-03-18
申请号：US13376247
申请日：2011-08-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823828 , H01L21/823878 , H01L27/1203 , H01L29/4908 , H01L29/78603 , H01L29/78612
摘要： The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括：SOI衬底和形成在SOI衬底上的MOSFET，其中SOI衬底以自顶向下的方式包括SOI层，第一掩埋绝缘体层，埋入半导体层，第二掩埋绝缘体层和半导体衬底，所述掩埋半导体层包括背栅区，所述背栅区包括掺杂有第一极性的掺杂剂的所述掩埋半导体层的一部分; MOSFET包括栅极堆叠和源极/漏极区，栅极堆叠形成在SOI层上，并且源极/漏极区域形成在栅极堆叠的相对侧的SOI层中; 并且所述背栅区域包括反掺杂区域，所述反掺杂区域与所述栅叠层自对准并且包括第二极性的掺杂剂，并且所述第二极性与所述第一极性相反。本公开的实施例可以用于调整MOSFET的阈值电压。

82. 发明授权

US08664054B2 Method for forming semiconductor structure 有权
标题翻译：半导体结构形成方法
公开(公告)号：US08664054B2
公开(公告)日：2014-03-04
申请号：US13381014
申请日：2011-04-18
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823828 , H01L29/7833 , H01L29/7847 , H01L29/7848
摘要： The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.
摘要翻译：本发明涉及一种形成半导体结构的方法，包括：提供包括形成在其上的虚拟栅极的半导体衬底，围绕伪栅极的间隔物，分别形成在虚拟栅极两侧的源区和漏区，以及形成在半导体衬底中并在虚拟栅极之下的沟道区; 去除虚拟门以形成门开口; 在闸门开口处形成应力材料层; 对所述半导体基板进行退火，所述应力材料层在退火时具有拉伸应力特性; 去除闸门开口中的应力材料层; 并在门开口形成门。通过上述步骤，可以将应力记忆技术应用于pMOSFET。

83. 发明授权

US08643119B2 Substantially L-shaped silicide for contact 有权
标题翻译：基本上L型硅化物进行接触
公开(公告)号：US08643119B2
公开(公告)日：2014-02-04
申请号：US12182212
申请日：2008-07-30
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.
摘要翻译：根据实施例的用于半导体器件的结构包括：基本上L形的硅化物元件，其包括基底构件和延伸构件，其中所述基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基部构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。

84. 发明授权

US08610275B2 Semiconductor contact structure including a spacer formed within a via and method of manufacturing the same 有权
标题翻译：包括在通孔内形成的间隔物的半导体接触结构及其制造方法
公开(公告)号：US08610275B2
公开(公告)日：2013-12-17
申请号：US12996721
申请日：2010-09-27
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L23/522 , H01L21/441
CPC分类号： H01L23/5226 , H01L21/76808 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate, a local interconnect structure connected to the semiconductor substrate, and at least one via stack structure electrically connected to the local interconnect structure, wherein the at least one via stack structure comprises a via having an upper via and a lower via, the width of the upper via being greater than that of the lower via; a via spacer formed closely adjacent to the inner walls of the lower via; an insulation layer covering the surfaces of the via and the via spacer; a conductive plug formed within the space surrounded by the insulation layer, and electrically connected to the local interconnect structure. The present invention is applicable to manufacture of a via stack in the filed of manufacturing semiconductor.
摘要翻译：本发明公开了一种半导体结构及其制造方法。半导体结构包括半导体衬底，连接到半导体衬底的局部互连结构以及电连接到局部互连结构的至少一个通孔堆叠结构，其中至少一个通孔堆叠结构包括具有上通孔和下通孔，上通孔的宽度大于下通孔的宽度; 形成在靠近下通道的内壁的通孔间隔件; 覆盖通孔和通孔间隔物的表面的绝缘层; 形成在由所述绝缘层包围的空间内并且电连接到所述局部互连结构的导电插塞。本发明可应用于半导体制造领域中的通孔叠层的制造。

85. 发明授权

US08598662B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08598662B2
公开(公告)日：2013-12-03
申请号：US13063745
申请日：2011-03-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803 , H01L29/7849
摘要： A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.
摘要翻译：半导体器件包括：位于绝缘层上的半导体衬底; 以及绝缘体，其位于所述绝缘层上并且嵌入所述半导体衬底中，其中所述绝缘体在其中向所述半导体衬底施加应力。一种形成半导体器件的方法包括：在绝缘层上形成半导体衬底; 在所述半导体衬底内形成空腔以暴露所述绝缘层; 在空腔中形成绝缘体，其中绝缘体在其中向半导体衬底施加应力。它有助于减少短沟道效应，源极/漏极区域的电阻和寄生电容。

86. 发明授权

US08598595B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08598595B2
公开(公告)日：2013-12-03
申请号：US13003873
申请日：2010-09-26
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/7848
摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET.
摘要翻译：本申请公开了一种半导体器件及其制造方法。半导体器件包括SOI衬底; 在所述SOI衬底上形成的半导体鳍片，所述半导体鳍片具有彼此相对并在所述SOI衬底的表面上向上并且在所述第二衬底的中心部分处开口的第一侧和第二侧; 侧和第一侧相对; 形成在所述翅片中并且在所述第二侧处在所述第一侧和所述沟槽之间的沟道区域; 源极和漏极区域形成在翅片中并夹着沟道区域; 以及形成在所述SOI衬底上并且邻近所述鳍的所述第一侧的栅极堆叠，其中所述栅极堆叠包括远离所述第一侧延伸并且邻近所述沟道区延伸的第一栅极电介质，所述第一侧并且邻近所述第一栅极电介质延伸，所述第二栅极电介质延伸远离所述第一侧并且横向邻近所述第一导体层的一侧;以及第二导体层，所述第二导体层从所述第一侧延伸并且横向相邻到第二栅极电介质的一侧。本发明的实施例可以应用于制造FinFET。

87. 发明授权

US08587066B2 Structure and method having asymmetrical junction or reverse halo profile for semiconductor on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) 失效
标题翻译：具有半导体绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）的不对称结或反向晕轮廓的结构和方法
公开(公告)号：US08587066B2
公开(公告)日：2013-11-19
申请号：US13407264
申请日：2012-02-28
申请人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Qingqing Liang , Haizhou Yin
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L27/1207 , H01L21/76251 , H01L21/8221 , H01L27/0688 , H01L29/66545
摘要： A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.
摘要翻译：提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中金属氮化物间隔物仅存在于第一沟道区的一侧。该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。还提供了具有反向卤素掺杂剂分布的结构。

88. 发明申请

US20130299885A1 FINFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： FINFET及其制造方法
公开(公告)号：US20130299885A1
公开(公告)日：2013-11-14
申请号：US13579192
申请日：2012-05-14
申请人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Wei He , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.
摘要翻译：公开了一种FinFET及其制造方法。 FinFET包括在半导体衬底上的蚀刻停止层; 在蚀刻停止层上的半导体鳍片; 栅极导体，其在与半导体鳍片的长度方向垂直的方向上延伸并覆盖半导体鳍片的至少两个侧面; 在栅极导体和半导体鳍片之间的栅介质层; 源极区和漏极区，分别设置在半导体鳍的两端; 以及与栅极电介质层下方的蚀刻停止层相邻的层间绝缘层，并且将栅极导体与蚀刻停止层和半导体鳍分离。 FinFET的鳍的高度近似等于用于形成半导体鳍的半导体层的厚度。

89. 发明申请

US20130285157A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130285157A1
公开(公告)日：2013-10-31
申请号：US13988192
申请日：2011-02-26
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/40 , H01L27/088
CPC分类号： H01L29/401 , H01L21/28518 , H01L21/76807 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure comprises: a first interlayer structure having a first dielectric layer and first contact vias; a second interlayer structure having a cap layer and second contact vias; and a third interlayer structure having a second dielectric layer and third contact vias. The first dielectric layer is flush with a gate stack or covers the gate stack, and the first contact vias penetrate through the first dielectric layer and are electrically connected with at least a portion of source/drain regions. The cap layer covers the first interlayer structure, and the second contact vias penetrate through the cap layer and are electrically connected with the first contact vias and the gate stack through a first liner. The second dielectric layer covers the second interlayer structure, and the third contact vias penetrate through the second dielectric layer and are electrically connected with the second contact vias through a second liner.
摘要翻译：半导体结构包括：具有第一介电层和第一接触通孔的第一层间结构; 具有盖层和第二接触通孔的第二层间结构; 以及具有第二介电层和第三接触通孔的第三层间结构。第一电介质层与栅极叠层齐平或覆盖栅极堆叠，并且第一接触通孔穿过第一电介质层并且与源/漏区的至少一部分电连接。盖层覆盖第一层间结构，并且第二接触通孔穿过盖层并且通过第一衬垫与第一接触通孔和栅极堆叠电连接。第二电介质层覆盖第二层间结构，第三接触通孔穿过第二电介质层，并通过第二衬垫与第二接触通孔电连接。

90. 发明申请

US20130276872A1 SOLAR CELL UNIT AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：太阳能电池单元及其制造方法
公开(公告)号：US20130276872A1
公开(公告)日：2013-10-24
申请号：US13864503
申请日：2013-04-17
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L31/0687 , H01L31/18
CPC分类号： H01L31/0687 , H01L31/022425 , H01L31/035281 , H01L31/0443 , H01L31/047 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A solar cell unit comprising a strip plate which has a third surface and a fourth surface opposite to the third surface, wherein a third doping region and a fourth doping region are arranged on the third surface and the fourth surface respectively, and a first doping region and a second doping region are arranged on side surfaces adjacent to the third surface and the fourth surface respectively; the types of impurities in the third doping region and the fourth doping region are contrary to one another; the surfaces of the first doping region and the second doping region have uniform doping type. Accordingly, the present invention further provides a method for manufacturing a solar cell unit.
摘要翻译：一种太阳能电池单元，包括具有第三表面和与第三表面相对的第四表面的带状板，其中第三掺杂区域和第四掺杂区域分别设置在第三表面和第四表面上，并且第一掺杂区域并且第二掺杂区域分别布置在与第三表面和第四表面相邻的侧表面上; 第三掺杂区域和第四掺杂区域中的杂质类型彼此相反; 第一掺杂区域和第二掺杂区域的表面具有均匀的掺杂类型。因此，本发明还提供一种太阳能电池单元的制造方法。

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