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81. 发明申请

US20180232171A1 System and Method for Providing a Back Door Communication Path Between Channels on Dual-Channel DIMMs 审中-公开
公开(公告)号：US20180232171A1
公开(公告)日：2018-08-16
申请号：US15429751
申请日：2017-02-10
申请人： DELL PRODUCTS, LP
发明人： Stuart Allen Berke , Bhyrav M. Mutnury , Vadhiraj Sankaranarayanan
IPC分类号： G06F3/06 , G06F13/16 , G06F13/40
CPC分类号： G06F3/0635 , G06F3/0619 , G06F3/0634 , G06F3/0683 , G06F13/16 , G06F13/4068
摘要： A dual-channel Dual In-Line Memory Module (DIMM) is configured to provide memory transactions on a first memory channel and a second memory channel. The dual-channel DIMM includes a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel, a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel, and a plurality of back door communication paths, each back door communication path being between a data bit of the first bank of DRAM devices and a corresponding data bit of the second bank of DRAM devices.

82. 发明授权

US09984741B2 System and method of transferring data over available pins 有权
公开(公告)号：US09984741B2
公开(公告)日：2018-05-29
申请号：US14933270
申请日：2015-11-05
申请人： Dell Products, LP
发明人： Vadhiraj Sankaranarayanan , Stuart Allen Berke , Bhyrav M. Mutnury
IPC分类号： G06F11/14 , G11C11/4093 , G11C11/4076 , G11C29/52 , G06F11/07 , G11C7/02 , G11C7/10 , G11C5/00 , G06F13/16 , G11C29/02 , G11C29/00
CPC分类号： G11C11/4093 , G06F11/073 , G06F11/0754 , G06F11/079 , G06F11/0793 , G06F13/1668 , G11C5/005 , G11C7/02 , G11C7/1066 , G11C11/4076 , G11C29/022 , G11C29/023 , G11C29/025 , G11C29/52 , G11C29/702
摘要： A system includes a memory device and a memory controller. The memory device has a data pin and a first available pin. The memory controller has a data pin coupled to the data pin of the memory device, and has a first available pin coupled to the first available pin of the memory device. The memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device.

83. 发明授权

US09946321B2 System and method to proactively screen component wear through time domain response profiling 有权
公开(公告)号：US09946321B2
公开(公告)日：2018-04-17
申请号：US14880761
申请日：2015-10-12
申请人： Dell Products, LP
发明人： Minchuan Wang , Stuart Allen Berke , Bhyrav M. Mutnury
IPC分类号： G06F13/12 , G06F1/32 , G06F11/30 , G06F13/42
CPC分类号： G06F1/3206 , G06F11/3048 , G06F11/3051 , G06F13/4282
摘要： A receiver of a serial communication channel including a memory to store an initial channel characteristic of the serial communication channel, a detector to measure a current channel characteristic of the serial communication channel, and a processor to compare the initial channel characteristic to the current channel characteristic, and to provide an indication when the difference between the initial channel characteristic to the current channel characteristic is greater than a threshold.

84. 发明申请

US20180034374A1 Configurable Multi-Rail Voltage Regulation with Coupled Inductor Power Steering 有权
公开(公告)号：US20180034374A1
公开(公告)日：2018-02-01
申请号：US15220616
申请日：2016-07-27
申请人： DELL PRODUCTS, LP
发明人： John J. Breen , Guangyong Zhu , Stuart Allen Berke , Abey K. Mathew
IPC分类号： H02M3/335 , G06F9/44
CPC分类号： H02M3/33507 , G06F9/4403 , H02M3/158 , H02M3/1584 , H02M2001/008 , H02M2001/009
摘要： A voltage regulator circuit comprises a plurality of voltage regulator phases, a first load output coupled to the plurality of voltage regulator phases for providing a first output voltage, a first coupling inductor having a first winding and a second winding, the first winding coupled in series between a first voltage regulator phase of the plurality of voltage regulator phases and the first load output, a second load output coupled to the second winding for providing a second output voltage, and a first switch coupled in series with the second winding. A method comprises detecting a startup event; determining an installed processor type; retrieving a configuration parameter value; providing a first output voltage at a first load output; providing, at a second load output coupled to the second winding, a second output voltage; and controlling a first duty cycle of a first switch coupled in series with the second winding.

85. 发明申请

US20170359205A1 Repeatable Backchannel Link Adaptation for High Speed Serial Interfaces 审中-公开
公开(公告)号：US20170359205A1
公开(公告)日：2017-12-14
申请号：US15688335
申请日：2017-08-28
申请人： DELL PRODUCTS, LP
发明人： Stuart Allen Berke , Bhyrav M. Mutnury , Minchuan Wang
IPC分类号： H04L25/06 , H04L25/03
CPC分类号： H04L25/061 , H04L25/03267 , H04L25/03885 , H04L25/03949
摘要： A receiver includes a plurality of equalization modules each configurable to provide a selectable compensation value to a data bit stream received by the receiver, and a control module configured to perform a plurality of back channel adaptations on the data bitstream to achieve a target bit error rate for the receiver, each back channel adaptation being associated with a set of compensation values of the equalization modules, determine a most common set of compensation values derived from the performance of the plurality of back channel adaptations, and determine an optimized set of compensation values based on the most common set of compensation values.

86. 发明申请

US20170133082A1 System and Method of Transferring Data over Available Pins 有权
公开(公告)号：US20170133082A1
公开(公告)日：2017-05-11
申请号：US14933270
申请日：2015-11-05
申请人： Dell Products, LP
发明人： Vadhiraj Sankaranarayanan , Stuart Allen Berke , Bhyrav M. Mutnury
IPC分类号： G11C11/4093 , G11C29/52 , G06F11/07 , G11C11/4076
CPC分类号： G11C11/4093 , G06F11/073 , G06F11/0754 , G06F11/079 , G06F11/0793 , G06F13/1668 , G11C5/005 , G11C7/02 , G11C7/1066 , G11C11/4076 , G11C29/022 , G11C29/023 , G11C29/025 , G11C29/52 , G11C29/702
摘要： A system includes a memory device and a memory controller. The memory device has a data pin and a first available pin. The memory controller has a data pin coupled to the data pin of the memory device, and has a first available pin coupled to the first available pin of the memory device. The memory controller transfers memory data on the first available pin of the memory controller, and the memory device receives memory data on the first available pin of the memory device.

87. 发明申请

US20170091137A1 System and Method to Blacklist Equalization Coefficients in a High-Speed Serial Interface 审中-公开
公开(公告)号：US20170091137A1
公开(公告)日：2017-03-30
申请号：US14868322
申请日：2015-09-28
申请人： Dell Products, LP
发明人： Stuart Allen Berke , Bhyrav M. Mutnury
IPC分类号： G06F13/42 , G06F13/368
CPC分类号： G06F13/4282 , G06F13/368
摘要： A serial interface comprises a receiver including a first input compensation module with a first setting that selects a first value from among a plurality of first values for a first input characteristic of the receiver, a memory to store a first blacklist value from among the first values, and a control module to select each of the first values, except for the first blacklist value, to evaluate an indication of a performance level of the receiver for each of the selected first values, and to select a particular first value based upon the indications of the performance level of the receiver.

88. 发明授权

US09313056B1 System aware transmitter adaptation for high speed serial interfaces 有权
标题翻译：适用于高速串行接口的系统感应发射机适配
公开(公告)号：US09313056B1
公开(公告)日：2016-04-12
申请号：US14535796
申请日：2014-11-07
申请人： Dell Products, LP
发明人： Stuart Allen Berke , Bhyrav M. Mutnury
IPC分类号： H04L25/03 , H04B3/04
CPC分类号： H04L25/03343 , H04B3/04 , H04L1/0033 , H04L25/0286 , H04L25/0292 , H04L25/03878 , H04L25/03885
摘要： A high-speed serial interface includes a transmitter having an output module with settings that select an output impedances of the output module and a tuning value for the output impedance, and a receiver having a plurality of compensation modules each to provide a selectable level of equalization to a data bitstream from the transmitter, and a control module that directs the transmitter to successively select each of the tuning values, that directs the compensation modules, for each tuning value, to successively select each of the levels of equalization, that evaluates an indication of a performance level of the receiver for each of the successively selected levels of equalization and for each of the tuning values, and that selects a particular tuning value based upon the indications of the performance level of the receiver.
摘要翻译：高速串行接口包括具有输出模块的发射器，输出模块具有选择输出模块的输出阻抗和输出阻抗的调谐值，以及具有多个补偿模块的接收器，每个补偿模块各自提供可选择的均衡电平涉及来自发射机的数据比特流，以及控制模块，其引导发射机连续选择针对每个调谐值引导补偿模块的每个调谐值，以逐次选择均衡等级的每个，其评估指示对于每个连续选择的均衡级别和每个调谐值的接收机的性能水平，并且基于接收机的性能水平的指示来选择特定调谐值。

89. 发明授权

US09274581B2 Date adjusted power budgeting for an information handling system 有权
标题翻译：日期调整功率预算的信息处理系统
公开(公告)号：US09274581B2
公开(公告)日：2016-03-01
申请号：US13924988
申请日：2013-06-24
申请人： Dell Products, LP
发明人： Stuart Allen Berke , John E. Jenne
IPC分类号： G06F1/32
CPC分类号： G06F1/32
摘要： An information handling system determines a system configuration including a hardware module, and determines an adjusted power budget for the hardware module. The adjusted power budget is based on a calculation including a difference between a date code read from the hardware module and a baseline date, a baseline power budget, a power reduction period and a power reduction interval. The calculation may optionally include a risk factor. In alternate embodiments, an adjusted power budget for a hardware module may be calculated by an order processing system for information handling systems, or by a planning tool for a data center which contains information handling systems.
摘要翻译：信息处理系统确定包括硬件模块的系统配置，并且确定用于硬件模块的经调整的功率预算。经调整的功率预算基于包括从硬件模块读取的日期代码与基线日期，基准功率预算，功率降低周期和功率降低间隔之间的差异的计算。计算可以可选地包括风险因素。在替代实施例中，用于硬件模块的经调整的功率预算可以由信息处理系统的订单处理系统或包含信息处理系统的数据中心的规划工具来计算。

90. 发明申请

US20160011802A1 System and Method for Enabling Transportability of a Non Volatile Dual Inline Memory Module 有权
标题翻译：用于实现非易失性双列直插式存储器模块的传输性的系统和方法
公开(公告)号：US20160011802A1
公开(公告)日：2016-01-14
申请号：US14326987
申请日：2014-07-09
申请人： Dell Products, LP
发明人： Stuart Allen Berke
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0631 , G06F3/0632 , G06F3/0679 , G06F12/00 , G06F12/0238 , G11C14/0018
摘要： A dual inline memory module includes a local memory and a non-volatile memory. The local memory stores data during normal operation of the dual inline memory module. The non-volatile memory includes a first portion and a second portion. The first portion stores the data located in the local memory in response to a power failure of an information handling system in communication with the dual inline memory module. The second portion stores configuration information for the dual inline memory module. The configuration information is utilized to set up the dual inline memory module in a new information handling system.
摘要翻译：双列直插式存储器模块包括本地存储器和非易失性存储器。本地存储器在双列直插式存储器模块的正常操作期间存储数据。非易失性存储器包括第一部分和第二部分。响应于与双列直插式存储器模块通信的信息处理系统的电源故障，第一部分存储位于本地存储器中的数据。第二部分存储双列直插式存储器模块的配置信息。配置信息用于在新的信息处理系统中建立双列直插式存储器模块。

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